SiE802DF Vishay Siliconix N-Channel 30-V (D-S) MOSFET FEATURES PRODUCT SUMMARY Halogen-free According to IEC 61249-2-21 a I (A) D Definition TrenchFET Gen II Power MOSFET Silicon Package e Ultra Low Thermal Resistance Using Top- V (V) R () Q (Typ.) Limit Limit DS DS(on) g Exposed PolarPAK Package for Double-Sided 0.0019 at V = 10 V 202 60 GS Cooling 30 50 nC Leadframe-Based New Encapsulated Package 0.0026 at V = 4.5 V 173 60 GS - Die Not Exposed - Same Layout Regardless of Die Size Package Drawing Low Q /Q Ratio Helps Prevent Shoot-Through www.vishay.com/doc 72945 gd gs 100 % R and UIS Tested PolarPAK g Compliant to RoHS directive 2002/95/EC 10 9 8 7 6 D G S S D 67 8 9 10 APPLICATIONS VRM DC/DC Conversion: Low-Side D Synchronous Rectification D DS G D G D G S S D 5 432 1 1 2 3 4 5 Top View Bottom View S Top surface is connected to pins 1, 5, 6, and 10 N-Channel MOSFET Ordering Information: SiE802DF-T1-E3 (Lead (Pb)-free) For Related Documents SiE802DF-T1-GE3 (Lead (Pb)-free and Halogen-free) www.vishay.com/ppg 72985 ABSOLUTE MAXIMUM RATINGS T = 25 C, unless otherwise noted A Parameter Symbol Limit Unit Drain-Source Voltage V 30 DS V V Gate-Source Voltage 20 GS 202 (Silicon Limit) T = 25 C C a 60 (Package Limit) a Continuous Drain Current (T = 150 C) I T = 70 C J D 60 C b, c T = 25 C 42.7 A b, c T = 70 C A 34.2 A Pulsed Drain Current I 100 DM a T = 25 C 60 C Continuous Source-Drain Diode Current I b, c S T = 25 C A 4.3 I Single Pulse Avalanche Current 50 AS L = 0.1 mH Avalanche Energy E 125 mJ AS T = 25 C 125 C T = 70 C 80 C Maximum Power Dissipation P W D b, c T = 25 C 5.2 A b, c T = 70 C A 3.3 Operating Junction and Storage Temperature Range T , T - 55 to 150 J stg C d, e 260 Soldering Recommendations (Peak Temperature) Notes: a. Package limited is 60 A. b. Surface Mounted on 1 x 1 FR4 board. c. t = 10 s. d. See Solder Profile (www.vishay.com/doc 73257). The PolarPAK is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: 72985 www.vishay.com S09-1337-Rev. E, 13-Jul-09 1SiE802DF Vishay Siliconix THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit a, b t 10 s R 20 24 Maximum Junction-to-Ambient thJA Maximum Junction-to-Case (Drain Top) R (Drain) 0.8 1 C/W thJC Steady State a, c R (Source) 2.2 2.7 Maximum Junction-to-Case (Source) thJC Notes: a. Surface Mounted on 1 x 1 FR4 board. b. Maximum under Steady State conditions is 68 C/W. c. Measured at source pin (on the side of the package). SPECIFICATIONS T = 25 C, unless otherwise noted J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static V = 0 V, I = 250 A Drain-Source Breakdown Voltage V 30 V GS D DS V Temperature Coefficient V /T 32.2 DS DS J I = 250 A mV/C D V Temperature Coefficient V /T - 6.4 GS(th) GS(th) J V V = V , I = 250 A Gate-Source Threshold Voltage 1.5 2.2 2.7 V GS(th) DS GS D I V = 0 V, V = 20 V Gate-Source Leakage 100 nA GSS DS GS V = 30 V, V = 0 V 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 30 V, V = 0 V, T = 55 C 10 DS GS J a I V 5 V, V = 10 V 25 A On-State Drain Current D(on) DS GS V = 10 V, I = 23.6 A 0.0016 0.0019 GS D a R Drain-Source On-State Resistance DS(on) V = 4.5 V, I = 21.3 A 0.0021 0.0026 GS D a g V = 15 V, I = 23.6 A 156 S Forward Transconductance fs DS D b Dynamic C Input Capacitance 7000 iss C V = 15 V, V = 0 V, f = 1 MHz Output Capacitance 1200 pF oss DS GS C Reverse Transfer Capacitance 500 rss V = 15 V, V = 10 V, I = 23.6 A 105 160 DS GS D Q Total Gate Charge g 50 75 nC Q V = 15 V, V = 4.5 V, I = 23.6 A Gate-Source Charge 21 gs DS GS D Q Gate-Drain Charge 14 gd R Gate Resistance f = 1 MHz 1.1 1.65 g t Turn-On Delay Time 45 70 d(on) t V = 15 V, R = 1.5 Rise Time 195 300 r DD L t I 10 A, V = 4.5 V, R = 1 Turn-Off Delay Time 45 70 d(off) D GEN g t Fall Time 20 30 f ns t Turn-On Delay Time 25 40 d(on) t V = 15 V, R = 1.5 Rise Time 20 30 r DD L t I 10 A, V = 10 V, R = 1 Turn-Off Delay Time 65 100 d(off) D GEN g t Fall Time 10 15 f Drain-Source Body Diode Characteristics I T = 25 C Continuous Source-Drain Diode Current 60 S C A a I 100 Pulse Diode Forward Current SM V I = 10 A Body Diode Voltage 0.8 1.2 V SD S t Body Diode Reverse Recovery Time 55 85 ns rr Q Body Diode Reverse Recovery Charge 66 105 nC rr I = 10 A, dI/dt = 100 A/s, T = 25 C F J t Reverse Recovery Fall Time 25 a ns t Reverse Recovery Rise Time 30 b Notes: a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 72985 2 S09-1337-Rev. E, 13-Jul-09