SiE832DF Vishay Siliconix N-Channel 40-V (D-S) MOSFET FEATURES PRODUCT SUMMARY Halogen-free According to IEC 61249-2-21 a I (A) D Definition Silicon Package TrenchFET Power MOSFET V (V) R () Q (Typ.) Limit Limit DS DS(on) g Ultra Low Thermal Resistance Using Top- 0.0055 at V = 10 V 103 Exposed PolarPAK Package for Double- 50 GS 40 25 nC Sided Cooling 0.007 at V = 4.5 V 91 50 GS Leadframe-Based New Encapsulated Package - Die Not Exposed Package Drawing www.vishay.com/doc 73398 - Same Layout Regardless of Die Size Low Q /Q Ratio Helps Prevent Shoot-Through gd gs PolarPAK 100 % R and UIS Tested 10 9 8 7 6 g D G S S D 67 8 9 10 Compliant to RoHS directive 2002/95/EC APPLICATIONS D VRM D DS G D Point-of-Load Synchronous Rectification G D G S S D 5 432 1 1 2 3 4 5 S Top View Bottom View Top surface is connected to pins 1, 5, 6, and 10 N-Channel MOSFET Ordering Information: SiE832DF-T1-E3 (Lead (Pb)-free) For Related Documents SiE832DF-T1-GE3 (Lead (Pb)-free and Halogen-free) www.vishay.com/ppg 74414 ABSOLUTE MAXIMUM RATINGS T = 25 C, unless otherwise noted A Parameter Symbol Limit Unit Drain-Source Voltage V 40 DS V V Gate-Source Voltage 20 GS 103 (Silicon Limit) T = 25 C C a 50 (Package Limit) a Continuous Drain Current (T = 150 C) I T = 70 C J D C 50 b, c T = 25 C 23.6 A b, c T = 70 C A A 18.9 Pulsed Drain Current I 80 DM a T = 25 C 50 C Continuous Source-Drain Diode Current I S b, c T = 25 C 4.3 A Single Pulse Avalanche Current I 35 AS L = 0.1 mH E Avalanche Energy 61 mJ AS T = 25 C 104 C T = 70 C 66 C P Maximum Power Dissipation W D b, c T = 25 C 5.2 A b, c T = 70 C 3.3 A Operating Junction and Storage Temperature Range T , T - 55 to 150 J stg C d, e 260 Soldering Recommendations (Peak Temperature) Notes: a. Package limited is 50 A. b. Surface Mounted on 1 x 1 FR4 board. c. t = 10 s. d. See Solder Profile (www.vishay.com/doc 73257). The PolarPAK is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: 74414 www.vishay.com S09-1338-Rev. C, 13-Jul-09 1SiE832DF Vishay Siliconix THERMAL RESISTANCE RATINGS Typical Maximum Parameter Symbol Unit a, b t 10 s R 20 24 Maximum Junction-to-Ambient thJA a R (Drain) 1 1.2 C/W Maximum Junction-to-Case (Drain Top) thJC Steady State a, c R (Source) 2.8 3.4 Maximum Junction-to-Case (Source) thJC Notes: a. Surface Mounted on 1 x 1 FR4 board. b. Maximum under Steady State conditions is 68 C/W. c. Measured at source pin (on the side of the package). SPECIFICATIONS T = 25 C, unless otherwise noted J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static V = 0 V, I = 250 A Drain-Source Breakdown Voltage V 40 V GS D DS V Temperature Coefficient V /T 43.1 DS DS J I = 250 A mV/C D V Temperature Coefficient V /T - 6.9 GS(th) GS(th) J V V = V , I = 250 A Gate-Source Threshold Voltage 1.5 2.2 3.0 V GS(th) DS GS D I V = 0 V, V = 20 V Gate-Source Leakage 100 nA GSS DS GS V = 40 V, V = 0 V 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 40 V, V = 0 V, T = 55 C 10 DS GS J a I V 5 V, V = 10 V 25 A On-State Drain Current D(on) DS GS V = 10 V, I = 14 A 0.0046 0.0055 GS D a R Drain-Source On-State Resistance DS(on) V = 4.5 V, I = 12 A 0.0058 0.007 GS D a g V = 15 V, I = 13.6 A 86 S Forward Transconductance fs DS D b Dynamic C Input Capacitance 3800 iss C V = 20 V, V = 0 V, f = 1 MHz Output Capacitance 510 pF oss DS GS C Reverse Transfer Capacitance 160 rss V = 20 V, V = 10 V, I = 20 A 51 77 DS GS D Q Total Gate Charge g 25 38 nC Q V = 20 V, V = 4.5 V, I = 20 A Gate-Source Charge 12 gs DS GS D Q Gate-Drain Charge 7 gd R Gate Resistance f = 1 MHz 1.1 1.7 g t Turn-On Delay Time 45 70 d(on) t V = 20 V, R = 2 Rise Time 260 400 r DD L t I 10 A, V = 4.5 V, R = 1 Turn-Off Delay Time 35 55 d(off) D GEN g t Fall Time 55 85 f t Turn-On Delay Time 15 25 d(on) ns t V = 20 V, R = 2 Rise Time 30 45 r DD L t I 10 A, V = 10 V, R = 1 Turn-Off Delay Time 35 55 d(off) D GEN g t Fall Time 10 15 f Drain-Source Body Diode Characteristics I T = 25 C Continuous Source-Drain Diode Current 50 S C A a I 80 Pulse Diode Forward Current SM V I = 10 A Body Diode Voltage 0.8 1.2 V SD S t Body Diode Reverse Recovery Time 85 130 ns rr Q Body Diode Reverse Recovery Charge 110 170 nC rr I = 10 A, dI/dt = 100 A/s, T = 25 C F J t Reverse Recovery Fall Time 64 a ns t Reverse Recovery Rise Time 21 b Notes: a. Pulse test pulse width 300 s, duty cycle 2 % b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 74414 2 S09-1338-Rev. C, 13-Jul-09