SIZ320DT-T1-GE3

3 m3 mmm SiZ320DT www.vishay.com Vishay Siliconix Dual N-Channel 25 V (D-S) MOSFETs FEATURES PowerPAIR 3 x 3 G 2 S TrenchFET Gen IV power MOSFETs 2 8 S 2 7 S 2 6 100 % R and UIS tested g 5 S /D 1 2 Optimized Q /Q ratio improves switching (Pin 9) gs gs D characteristics 1 1 Material categorization: 2 G 1 3 D for definitions of compliance please see 1 11 4 D 1 www.vishay.com/doc 99912 D 1 Top View Bottom View D APPLICATIONS 1 PRODUCT SUMMARY CPU core power CHANNEL-1 CHANNEL-2 G 1 Computer / server peripherals V (V) 25 25 DS N-Channel 1 S /D R max. ( ) at V = 10 V 0.00830 0.00424 1 2 DS(on) GS POL MOSFET R max. ( ) at V = 4.5 V 0.01270 0.00658 DS(on) GS Synchronous buck converter Q typ. (nC) 4.3 7.9 g G 2 Telecom DC/DC a, g I (A) 30 40 N-Channel 2 D MOSFET S Configuration Dual 2 ORDERING INFORMATION Package PowerPAIR 3 x 3 Lead (Pb)-free and halogen-free SiZ320DT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1 CHANNEL-2 UNIT Drain-source voltage V 25 25 DS V Gate-source voltage V +16, -12 +16, -12 GS a a T = 25 C 30 40 C a a T = 70 C 29.2 40 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 17.2 24.8 A b, c b, c T = 70 C 13.7 19.8 A A Pulsed drain current (100 s pulse width) I 80 120 DM T = 25 C 13.9 25.8 C Continuous source drain diode current I S b, c b, c T = 25 C 3.1 3.5 A Single pulse avalanche current I 12 18 AS L = 100 mH Single pulse avalanche energy E 7.2 16.2 mJ AS T = 25 C 16.7 31 C T = 70 C 10.7 20 C Maximum power dissipation P W D b, c b, c T = 25 C 3.7 4.2 A b, c b, c T = 70 C 2.4 2.7 A Operating junction and storage temperature range T , T -55 to +150 J stg C d Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 27 34 24 30 thJA C/W Maximum junction-to-case (drain) Steady state R 67.5 3.24 thJC Notes a. Package limited b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 69 C/W for channel-1 and 64 C/W for channel-2 g. T = 25 C C S17-0302-Rev. A, 27-Feb-17 Document Number: 68279 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 3 mm3 mmSiZ320DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static V = 0 V, I = 250 A Ch-1 25 - - GS D Drain-source breakdown voltage V V DS V = 0 V, I = 250 A Ch-2 25 - - GS D I = 250 A Ch-1 - 17 - D V Temperature coefficient V /T DS DS J I = 250 A Ch-2 - 16 - D mV/C I = 250 A Ch-1 - 4.2 - D V Temperature coefficient V /T GS(th) GS(th) J I = 250 A Ch-2 - 4.5 - D V = V , I = 250 A Ch-1 1.1 - 2.4 DS GS D Gate threshold voltage V V GS(th) V = V , I = 250 A Ch-2 1.1 - 2.4 DS GS D Ch-1 - - 100 Gate source leakage I V = 0 V, V = +16 V, -12 V nA GSS DS GS Ch-2 - - 100 V = 25 V, V = 0 V Ch-1 - - 1 DS GS V = 25 V, V = 0 V Ch-2 - - 1 DS GS Zero gate voltage drain current I A DSS V = 25 V, V = 0 V, T = 55 C Ch-1 - - 10 DS GS J V = 25 V, V = 0 V, T = 55 C Ch-2 - - 10 DS GS J V 5 V, V = 10 V Ch-1 15 - - DS GS b On-state drain current I A D(on) V 5 V, V = 10 V Ch-2 15 - - DS GS V = 10 V, I = 8 A Ch-1 - 0.00690 0.00830 GS D V = 10 V, I = 10 A Ch-2 - 0.00353 0.00424 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 5 A Ch-1 - 0.01010 0.01270 GS D V = 4.5 V, I = 8 A Ch-2 - 0.00526 0.00658 GS D V = 10 V, I = 8 A Ch-1 - 45 - GS D b Forward transconductance g S fs V = 10 V, I = 10 A Ch-2 - 68 - GS D a Dynamic Ch-1 - 660 - Input capacitance C iss Ch-2 - 1370 - Ch-1 - 230 - Channel-1 Output capacitance C pF oss V = 12.5 V, V = 10 V, f = 1 MHz DS GS Ch-2 - 410 - Ch-1 - 35 - Channel-2 Reverse transfer capacitance C rss V = 12.5 V, V = 10 V, f = 1 MHz Ch-2 - 55 - DS GS Ch-1 - 0.056 0.115 C /C ratio rss iss Ch-2 - 0.04 0.08 V = 12.5 V, V = 10 V, I = 15 A Ch-1 - 9.5 15 DS GS D V = 12.5 V, V = 10 V, I = 20 A Ch-2 - 17.8 26.7 DS GS D Total gate charge Q g V = 12.5 V, V = 4.5 V, I = 15 A Ch-1 - 4.3 8.9 DS GS D V = 12.5 V, V = 4.5 V, I = 20 A Ch-2 - 7.9 11.9 DS GS D Ch-1 - 1.8 - Channel-1 Gate-source charge Q nC gs V = 12.5 V, V = 4.5 V, I = 15 A DS GS D Ch-2 - 3.8 - Ch-1 - 0.8 - Channel-2 Gate-drain charge Q gd V = 12.5 V, V = 4.5 V, I = 20 A DS GS D Ch-2 - 1.2 - Ch-1 - 4.6 - Output charge Q V = 12.5 V, V = 0 V oss DS GS Ch-2 - 8.1 - Ch-1 0.26 1.3 2.6 Gate resistance R f = 1 MHz g Ch-2 0.2 1 2 S17-0302-Rev. A, 27-Feb-17 Document Number: 68279 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000