SiZ328DT-T1-GE3 Vishay

3 m3 mmm SiZ328DT www.vishay.com Vishay Siliconix Dual N-Channel 25 V (D-S) MOSFETs FEATURES PowerPAIR 3 x 3 G 2 S TrenchFET Gen IV power MOSFETs 2 8 S 2 7 S 2 6 100 % R and UIS tested g 5 S /D 1 2 Optimized Q /Q ratio improves switching (Pin 9) gs gs D characteristics 1 1 Material categorization: 2 G 1 3 D for definitions of compliance please see 1 11 4 D 1 www.vishay.com/doc 99912 D 1 Top View Bottom View D APPLICATIONS 1 PRODUCT SUMMARY CPU core power CHANNEL-1 CHANNEL-2 G 1 Computer / server peripherals V (V) 25 25 DS N-Channel 1 S /D R max. ( ) at V = 10 V 0.0150 0.0100 1 2 DS(on) GS POL MOSFET R max. ( ) at V = 4.5 V 0.0250 0.0150 DS(on) GS Synchronous buck converter Q typ. (nC) 2.1 3.5 g G 2 Telecom DC/DC g a I (A) 25.3 30 N-Channel 2 D MOSFET S Configuration Dual 2 ORDERING INFORMATION Package PowerPAIR 3 x 3 Lead (Pb)-free and halogen-free SiZ328DT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1 CHANNEL-2 UNIT Drain-source voltage V 25 25 DS V Gate-source voltage V +16, -12 +16, -12 GS a T = 25 C 25.3 30 C T = 70 C 20.2 25.5 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 11.1 15 A b, c b, c T = 70 C 8.9 12 A A Pulsed drain current (100 s pulse width) I 40 50 DM T = 25 C 12.6 13.5 C Continuous source drain diode current I S b, c b, c T = 25 C 2.4 3 A Single pulse avalanche current I 711 AS L = 0.1 mH Single pulse avalanche energy E 2.5 6.1 mJ AS T = 25 C 15 16.2 C T = 70 C 9.6 10.4 C Maximum power dissipation P W D b, c b, c T = 25 C 2.9 3.6 A b, c b, c T = 70 C 1.8 2.3 A Operating junction and storage temperature range T , T -55 to +150 J stg C d Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 35 43 28 35 thJA C/W Maximum junction-to-case (drain) Steady state R 6.7 8.3 6.3 7.7 thJC Notes a. Package limited b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR 3 x 3 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 80 C/W for channel-1 and 69 C/W for channel-2 g. T = 25 C C S19-0938-Rev. B, 04-Nov-2019 Document Number: 76059 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 3 mm3 mm SiZ328DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static V = 0 V, I = 250 A Ch-1 25 - - GS D Drain-source breakdown voltage V V DS V = 0 V, I = 250 A Ch-2 25 - - GS D I = 250 A Ch-1 - 19 - D V Temperature coefficient V /T DS DS J I = 250 A Ch-2 - 18 - D mV/C I = 250 A Ch-1 - -4.1 - D V Temperature coefficient V /T GS(th) GS(th) J I = 250 A Ch-2 - -4.3 - D V = V , I = 250 A Ch-1 1.1 - 2.5 DS GS D Gate threshold voltage V V GS(th) V = V , I = 250 A Ch-2 1.1 - 2.5 DS GS D V = 0 V, V = +16 V, -12 V Ch-1 - - 100 DS GS Gate source leakage I nA GSS V = 0 V, V = +16 V, -12 V Ch-2 - - 100 DS GS V = 25 V, V = 0 V Ch-1 - - 1 DS GS V = 25 V, V = 0 V Ch-2 - - 1 DS GS Zero gate voltage drain current I A DSS V = 25 V, V = 0 V, T = 55 C Ch-1 - - 5 DS GS J V = 25 V, V = 0 V, T = 55 C Ch-2 - - 5 DS GS J V 5 V, V = 10 V Ch-1 10 - - DS GS b On-state drain current I A D(on) V 5 V, V = 10 V Ch-2 10 - - DS GS V = 10 V, I = 5 A Ch-1 - 0.0120 0.0150 GS D V = 10 V, I = 5 A Ch-2 - 0.0080 0.0100 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 5 A Ch-1 - 0.0175 0.0250 GS D V = 4.5 V, I = 5 A Ch-2 - 0.0120 0.0150 GS D V = 10 V, I = 10 A Ch-1 - 25 - DS D b Forward transconductance g S fs V = 10 V, I = 10 A Ch-2 - 42 - DS D a Dynamic Ch-1 - 325 - Input capacitance C iss Ch-2 - 600 - Ch-1 - 115 - Channel-1 Output capacitance C pF oss V = 10 V, V = 0 V, f = 1 MHz DS GS Ch-2 - 230 - Ch-1 - 20 - Channel-2 Reverse transfer capacitance C rss V = 10 V, V = 0 V, f = 1 MHz Ch-2 - 31 - DS GS Ch-1 - 0.060 0.120 C /C ratio rss iss Ch-2 - 0.052 0.110 V = 10 V, V = 10 V, I = 5 A Ch-1 - 4.6 6.9 DS GS D V = 10 V, V = 10 V, I = 5 A Ch-2 - 7.5 11.3 DS GS D Total gate charge Q g V = 10 V, V = 4.5 V, I = 5 A Ch-1 - 2.1 3.2 DS GS D V = 10 V, V = 4.5 V, I = 5 A Ch-2 - 3.5 5.3 DS GS D Ch-1 - 0.95 - Channel-1 Gate-source charge Q nC gs V = 10 V, V = 4.5 V, I = 5 A DS GS D Ch-2 - 1.63 - Ch-1 - 0.37 - Channel-2 Gate-drain charge Q gd V = 10 V, V = 4.5 V, I = 5 A DS GS D Ch-2 - 0.54 - Ch-1 - 1.7 - Output charge Q V = 10 V, V = 0 V oss DS GS Ch-2 - 3.4 - Ch-1 0.28 1.4 2.8 Gate resistance R f = 1 MHz g Ch-2 0.18 0.9 1.8 S19-0938-Rev. B, 04-Nov-2019 Document Number: 76059 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000