SiZ914DT Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFETs FEATURES PRODUCT SUMMARY TrenchFET Gen IV Power MOSFETs g V (V) R ( ) (Max.) Q (Typ.) I (A) 100 % R and UIS Tested DS DS(on) g D g Material categorization: a 0.00640 at V = 10 V GS 16 Channel-1 30 7.2 nC For definitions of compliance please see a 0.01000 at V = 4.5 V GS 16 www.vishay.com/doc 99912 a 0.00137 at V = 10 V GS 40 Channel-2 30 30.1 nC APPLICATIONS D 1 a 0.00194 at V = 4.5 V GS 40 CPU Core Power Computer/Server Peripherals PowerPAIR 6 x 5 Synchronous Buck Converter Pin 1 G 1 G 1 POL 5 mm 1 D 1 N-Channel 1 2 Telecom DC/DC D 1 S /D 1 2 MOSFET 3 D D 1 1 4 G 2 S /D 1 2 Schottky Pin 9 8 G Diode 2 S 2 7 N-Channel 2 6 mm 6 MOSFET 5 S 2 Ordering Information: SiZ914DT-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A Parameter Symbol Channel-1Channel-2Unit V Drain-Source Voltage 30 DS V V Gate-Source Voltage GS + 20, - 16 a a T = 25 C 16 40 C a a T = 70 C 16 40 C Continuous Drain Current (T = 150 C) I J D a, b, c a, b, c T = 25 C A 16 40 b, c b, c T = 70 C 15.5 38.8 A A I Pulsed Drain Current (t = 100 s) 80 100 DM T = 25 C C 19 28 I Continuous Source Drain Diode Current S b, c b, c T = 25 C 3.25 4.3 A I Single Pulse Avalanche Current 10 20 AS L = 0.1 mH E Single Pulse Avalanche Energy mJ AS 520 T = 25 C 22.7 100 C T = 70 C 14.5 64 C Maximum Power Dissipation P W D b, c b, c T = 25 C A 3.9 5.2 b, c b, c T = 70 C 2.5 3.3 A T , T Operating Junction and Storage Temperature Range - 55 to 150 J stg C d, e Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS Channel-1 Channel-2 Parameter Symbol Typ. Max. Typ. Max. Unit b, f R t 10 s 25 32 19 24 Maximum Junction-to-Ambient thJA C/W R Maximum Junction-to-Case (Drain) Steady State 4.4 5.5 1 1.25 thJC Notes: a. Package limited b. Surface mounted on 1 x 1 FR4 board. c. t = 10 s. d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 62 C/W for channel-1 and 55 C/W for channel-2. g. T = 25 C. C Document Number: 62905 www.vishay.com For technical questions, contact: pmostechsupport vishay.com S13-2181-Rev. A, 14-Oct-13 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000SiZ914DT Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J Parameter Symbol Test Conditions Min. Typ.Max.Unit Static V = 0 V, I = 250 A Ch-1 30 GS D V Drain-Source Breakdown Voltage V DS V = 0 V, I = 250 A Ch-2 30 GS D V = V , I = 250 A Ch-1 1.2 2.4 DS GS D V Gate Threshold Voltage V GS(th) V = V , I = 250 A Ch-2 1 2.4 DS GS D Ch-1 100 Gate Source Leakage I V = 0 V, V = 20 V, - 16 V nA GSS DS GS Ch-2 100 V = 30 V, V = 0 V Ch-1 1 DS GS V = 30 V, V = 0 V Ch-2 60 240 A DS GS Zero Gate Voltage Drain Current I DSS V = 30 V, V = 0 V, T = 55 C Ch-1 5 DS GS J V = 30 V, V = 0 V, T = 55 C Ch-2 0.5 5 mA DS GS J V 5 V, V = 10 V Ch-1 20 DS GS b I A On-State Drain Current D(on) V 5 V, V = 10 V Ch-2 25 DS GS V = 10 V, I = 19 A Ch-1 0.00530 0.00640 GS D V = 10 V, I = 20 A Ch-2 0.00114 0.00137 GS D b R Drain-Source On-State Resistance DS(on) V = 4.5 V, I = 15 A Ch-1 0.00800 0.01000 GS D V = 4.5 V, I = 20 A Ch-2 0.00155 0.00194 GS D V = 10 V, I = 19 A Ch-1 55 DS D b g S Forward Transconductance fs V = 10 V, I = 20 A Ch-2 68 DS D a Dynamic Ch-1 1208 C Input Capacitance iss Ch-2 5603 Channel-1 Ch-1 375 C Output Capacitance pF oss V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-2 2202 Ch-1 30 Channel-2 C Reverse Transfer Capacitance rss Ch-2 168 V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-1 0.025 0.050 C /C Ratio rss iss Ch-2 0.032 0.064 V = 15 V, V = 10 V, I = 20 A Ch-1 17 26 DS GS D V = 15 V, V = 10 V, I = 20 A Ch-2 66 99 DS GS D Q Total Gate Charge g Ch-1 7.2 11 Channel-1 Ch-2 30.1 45.2 V = 15 V, V = 4.5 V, I = 20 A DS GS D Ch-1 3.6 Q nC Gate-Source Charge gs Ch-2 10.9 Channel-2 Ch-1 0.94 V = 15 V, V = 4.5 V, I = 20 A DS GS D Q Gate-Drain Charge gd Ch-2 3.8 Ch-1 10 Q V = 15 V, V = 0 V Output Charge oss DS GS Ch-2 60 Ch-1 0.5 2.5 5 R Gate Resistance f = 1 MHz g Ch-2 0.2 1 2 Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test pulse width 300 s, duty cycle 2 %. www.vishay.com Document Number: 62905 For technical questions, contact: pmostechsupport vishay.com 2 S13-2181-Rev. A, 14-Oct-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000