New Product SiZ918DT Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFETs FEATURES PRODUCT SUMMARY TrenchFET Power MOSFETs V (V) R ( ) (Max.) I (A) Q (Typ.) 100 % R and UIS Tested DS DS(on) D g g Material categorization: a 0.0120 at V = 10 V GS 16 For definitions of compliance please see Channel-1 30 6.8 nC a 0.0145 at V = 4.5 V www.vishay.com/doc 99912 GS 16 a 0.0037 at V = 10 V APPLICATIONS GS 28 Channel-2 30 32 nC a Notebook System Power 0.0045 at V = 4.5 V GS 28 POL Synchronous Buck Converter D 1 PowerPAIR 6 x 5 Pin 1 G 1 5 mm 1 D 1 2 G D 1 1 3 D D 1 1 N-Channel 1 4 S /D MOSFET 1 2 G 2 S /D 1 2 Pin 9 8 S 2 7 6 mm 6 G 2 5 N-Channel 2 MOSFET Ordering Information: SiZ918DT-T1-GE3 (Lead (Pb)-free and Halogen-free) S 2 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A Parameter Symbol Channel-1Channel-2Unit V 30 Drain-Source Voltage DS V Gate-Source Voltage V 20 GS a a T = 25 C 16 28 C a a T = 70 C 16 28 C Continuous Drain Current (T = 150 C) I J D b, c a, b, c T = 25 C 14.3 26 A b, c a, b, c T = 70 C A 11.4 21 A I Pulsed Drain Current (t = 300 s) 50 110 DM a a T = 25 C 16 28 C I Continuous Source Drain Diode Current S b, c b, c T = 25 C A 3.4 4.3 I Single Pulse Avalanche Current 18 35 AS L = 0.1 mH Single Pulse Avalanche Energy E 16 61 mJ AS T = 25 C 29 100 C T = 70 C 18 64 C P W Maximum Power Dissipation D b, c b, c T = 25 C A 4.2 5.2 b, c b, c T = 70 C A 2.7 3.3 T , T Operating Junction and Storage Temperature Range - 55 to 150 J stg C d, e Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS Channel-1 Channel-2 Parameter Symbol Typ. Max. Typ. Max. Unit b, f t 10 s R 24 30 19 24 Maximum Junction-to-Ambient thJA C/W R Maximum Junction-to-Case (Drain) Steady State 3.4 4.3 1 1.25 thJC Notes: a. Package limited. b. Surface mounted on 1 x 1 FR4 board. c. t = 10 s. d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 65 C/W for channel-1 and 55 C/W for channel-2. Document Number: 63783 For more information please contact: pmostechsupport vishay.com www.vishay.com S12-0543 Rev. A, 12-Mar-12 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000New Product SiZ918DT Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J Parameter Symbol Test Conditions Min. Typ.Max.Unit Static V = 0 V, I = 250 A Ch-1 30 GS D V Drain-Source Breakdown Voltage V DS V = 0 V, I = 250 A Ch-2 30 GS D I = 250 A Ch-1 33 D V Temperature Coefficient V /T DS DS J I = 250 A Ch-2 37 D mV/C I = 250 A Ch-1 - 5 D V Temperature Coefficient V /T GS(th) GS(th) J I = 250 A Ch-2 - 7.5 D V = V , I = 250 A Ch-1 1 2.2 DS GS D V Gate Threshold Voltage V GS(th) V = V , I = 250 A Ch-2 1.2 2.2 DS GS D Ch-1 100 I V = 0 V, V = 20 V Gate Source Leakage nA GSS DS GS Ch-2 100 V = 30 V, V = 0 V Ch-1 1 DS GS V = 30 V, V = 0 V Ch-2 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 30 V, V = 0 V, T = 55 C Ch-1 5 DS GS J V = 30 V, V = 0 V, T = 55 C Ch-2 5 DS GS J V 5 V, V = 10 V Ch-1 20 DS GS b I A On-State Drain Current D(on) V 5 V, V = 10 V Ch-2 20 DS GS V = 10 V, I = 13.8 A Ch-1 0.0100 0.0120 GS D V = 10 V, I = 20 A Ch-2 0.0030 0.0037 GS D b R Drain-Source On-State Resistance DS(on) V = 4.5 V, I = 12.6 A Ch-1 0.0120 0.0145 GS D V = 4.5 V, I = 20 A Ch-2 0.0035 0.0045 GS D V = 10 V, I = 13.8 A Ch-1 47 DS D b g S Forward Transconductance fs V = 10 V, I = 20 A Ch-2 116 DS D a Dynamic Ch-1 790 C Input Capacitance iss Channel-1 Ch-2 3830 V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-1 190 C Output Capacitance pF oss Ch-2 670 Channel-2 Ch-1 76 V = 15 V, V = 0 V, f = 1 MHz DS GS C Reverse Transfer Capacitance rss Ch-2 315 V = 15 V, V = 10 V, I = 13.8 A Ch-1 14 21 DS GS D V = 15 V, V = 10 V, I = 20 A Ch-2 67.3 105 DS GS D Total Gate Charge Q g Ch-1 6.8 11 Channel-1 Ch-2 32 48 nC V = 15 V, V = 4.5 V, I = 13.8 A DS GS D Ch-1 2.6 Q Gate-Source Charge gs Ch-2 10.8 Channel-2 Ch-1 1.9 V = 15 V, V = 4.5 V, I = 20 A DS GS D Q Gate-Drain Charge gd Ch-2 9.3 Ch-1 0.4 2 4 R Gate Resistance f = 1 MHz g Ch-2 0.2 1.1 2.2 Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test pulse width 300 s, duty cycle 2 %. www.vishay.com For more information please contact: pmostechsupport vishay.com Document Number: 63783 2 S12-0543 Rev. A, 12-Mar-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000