SiZF914DT www.vishay.com Vishay Siliconix Dual N-Channel 25 V (D-S) MOSFET with Schottky Diode FEATURES TrenchFET Gen IV power MOSFET SkyFET low side MOSFET with integrated Schottky G return/S pin for enhancing high side driving 1 1 100 % R and UIS tested g Material categorization: for definitions of compliance please see www.vishay.com/doc 99912 V /D APPLICATIONS N-Channel 1 IN 1 MOSFET CPU core power PRODUCT SUMMARY G /G HS 1 Computer / server peripherals CHANNEL-1 CHANNEL-2 G Return/S V /S -D POL 1 1 SW 1 2 V (V) 25 25 DS Synchronous buck converter R max. ( ) at V = 10 V 0.00380 0.00090 DS(on) GS R max. ( ) at V = 4.5 V 0.00620 0.00150 Telecom DC/DC DS(on) GS Schottky G /G Q typ. (nC) 6.6 31 LS 2 g Diode a I (A) 40 60 D N-Channel 2 Configuration Dual MOSFET GND/S 2 ORDERING INFORMATION Package PowerPAIR 6 x 5F Lead (Pb)-free and halogen-free SiZF914DT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1CHANNEL-2UNIT Drain-source voltage V 25 25 DS V Gate-source voltage V +20, -16 +16, -12 GS a a T = 25 C 40 60 C a a T = 70 C 40 60 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 23.5 52 A b, c b, c T = 70 C 19 42 A A Pulsed drain current (t = 100 s) I 130 110 DM a T = 25 C 22 60 C Continuous source-drain diode current I S b, c b, c T = 25 C 2.8 6.7 A Single pulse avalanche current I 20 34 AS L = 0.1 mH Single pulse avalanche energy E 20 58 mJ AS T = 25 C 26.6 60 C T = 70 C 17 38 C Maximum power dissipation P W D b, c b, c T = 25 C 3.4 4 A b, c b, c T = 70 C 2.2 2.6 A Operating junction and storage temperature range T , T -55 to +150 J stg C d, e Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 30 37 25 31 thJA C/W Maximum junction-to-case (source) Steady state R 3.8 4.7 1.7 2.1 thJC Notes a. Package limited b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 77 C/W for channel-1 and 68 C/W for channel-2 S17-1735 Rev. A, 20-Nov-17 Document Number: 75978 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 SiZF914DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAX.UNIT Static Ch-1 25 - - Drain-source breakdown voltage V V = 0 V, I = 250 A DS GS D Ch-2 25 - - V Ch-1 1.1 - 2.4 Gate-source threshold voltage V V = V , I = 250 A GS(th) DS GS D Ch-2 1.1 - 2.2 V = 0 V, V = +20 V, -16 V Ch-1 - - 100 DS GS Gate-source leakage I nA GSS V = 0 V, V = +16 V, -12 V Ch-2 - - 100 DS GS Ch-1 - - 1 V = 25 V, V = 0 V DS GS Ch-2 - 30 350 Zero Gate voltage drain current I A DSS Ch-1 - - 5 V = 25 V, V = 0 V, T = 55 C DS GS J Ch-2 - 200 3000 Ch-1 20 - - b On-state drain current I V 5 V, V = 10 V A D(on) DS GS Ch-2 20 - - V = 10 V, I = 10 A Ch-1 - 0.00270 0.00380 GS D V = 10 V, I = 10 A Ch-2 - 0.00060 0.00090 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 5 A Ch-1 - 0.00410 0.00620 GS D V = 4.5 V, I = 5 A Ch-2 - 0.00095 0.00150 GS D V = 10 V, I = 20 A Ch-1 - 45 - DS D b Forward transconductance g S fs V = 10 V, I = 20 A Ch-2 105 - DS D a Dynamic Ch-1 - 1050 - Input capacitance C iss Ch-2 - 4670 - Channel-1 Ch-1 - 510 - Output capacitance C V = 10 V, V = 0 V, f = 1 MHz pF oss DS GS Ch-2 - 1650 - Ch-1 - 47 - Channel-2 Reverse transfer capacitance C rss Ch-2 - 370 - V = 10 V, V = 0 V, f = 1 MHz DS GS Ch-1 - 0.036 0.072 C /C ratio rss iss Ch-2 0.062 0.125 Ch-1 - 14 21 V = 10 V, V = 10 V, I = 10 A DS GS D Ch-2 - 65 98 Total gate charge Q g Ch-1 6.6 10 Channel-1 Ch-2 - 31 47 V = 10 V, V = 4.5 V, I = 10 A DS GS D Ch-1 - 3.2 - Gate-source charge Q nC gs Ch-2 - 10.2 - Channel-2 Ch-1 - 1.2 - V = 10 V, V = 4.5 V, I = 10 A DS GS D Gate-drain charge Q gd Ch-2 - 6.4 - Ch-1 - 7.5 - Output charge Q V = 10 V, V = 0 V oss DS GS Ch-2 - 27 - Ch-1 0.2 1 2 Gate resistance R f = 1 MHz g Ch-2 0.1 0.3 0.6 S17-1735 Rev. A, 20-Nov-17 Document Number: 75978 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000