W25Q128JVSIM

W25Q128JV-DTR 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI & DTR For Industrial & Industrial Plus Grade Publication Release Date: March 02, 2018 -Revision C W25Q128JV-DTR Table of Contents 1. GENERAL DESCRIPTIONS ............................................................................................................. 5 2. FEATURES ....................................................................................................................................... 5 3. PACKAGE TYPES AND PIN CONFIGURATIONS ........................................................................... 6 3.1 Pin Configuration SOIC 208-mil ........................................................................................... 6 3.2 Pad Configuration WSON 6x5-mm / 8x6-mm ...................................................................... 6 3.3 Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm ................................................... 6 3.4 Pin Configuration SOIC 300-mil ........................................................................................... 7 3.5 Pin Description SOIC 300-mil ............................................................................................... 7 3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8 3.7 Ball Description TFBGA 8x6-mm ......................................................................................... 8 4. PIN DESCRIPTIONS ........................................................................................................................ 9 4.1 Chip Select (/CS) .................................................................................................................. 9 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 9 4.3 Write Protect (/WP) .............................................................................................................. 9 4.4 HOLD (/HOLD) ..................................................................................................................... 9 4.5 Serial Clock (CLK) ................................................................................................................ 9 4.6 Reset (/RESET) .................................................................................................................... 9 5. BLOCK DIAGRAM .......................................................................................................................... 10 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11 6.1 SPI / QPI Operations .......................................................................................................... 11 6.1.1 Standard SPI Instructions ..................................................................................................... 11 6.1.2 Dual SPI Instructions ............................................................................................................ 11 6.1.3 Quad SPI Instructions ........................................................................................................... 12 6.1.4 QPI Instructions .................................................................................................................... 12 6.1.5 SPI / QPI DTR Read Instructions ......................................................................................... 12 6.1.6 Hold Function ....................................................................................................................... 12 6.1.7 Software Reset & Hardware /RESET pin .............................................................................. 13 6.2 Write Protection .................................................................................................................. 14 6.2.1 Write Protect Features ......................................................................................................... 14 7. STATUS AND CONFIGURATION REGISTERS ............................................................................ 15 7.1 Status Registers ................................................................................................................. 15 7.1.1 Erase/Write In Progress (BUSY) Status Only ................................................................ 15 7.1.2 Write Enable Latch (WEL) Status Only .......................................................................... 15 7.1.3 Block Protect Bits (BP2, BP1, BP0) Volatile/Non-Volatile Writable ................................ 15