W66BM6NB / W66CM2NQ 2Gb / 4Gb LPDDR4X Table of Contents- 1. GENERAL DESCRIPTION ............................................................................................................................................ 5 2. FEATURES .................................................................................................................................................................... 5 3. ORDER INFORMATION ................................................................................................................................................ 5 4. BALL ASSIGNMENT ..................................................................................................................................................... 6 4.1 Single-Die-Package (SDP) WFBGA 200 Ball Assignment ............................................................................................. 6 4.2 Dual-Die-Package (DDP) WFBGA 200 Ball Assignment ............................................................................................... 7 5. BALL CONFIGURATION ............................................................................................................................................... 8 5.1 Ball Description .............................................................................................................................................................. 8 5.2 Addressing Table ........................................................................................................................................................... 9 6. BLOCK DIAGRAM ....................................................................................................................................................... 10 6.1 Block diagram of single chip ........................................................................................................................................ 10 6.2 Block diagram of Dual-Die-Package (DDP) ................................................................................................................. 11 7. FUNCTIONAL DESCRIPTION ..................................................................................................................................... 12 7.1 Simplified LPDDR4X State Diagram ............................................................................................................................ 12 7.1.1 Simplified Bus Interface State Diagram ....................................................................................................................... 13 7.2 Power-up, Initialization, and Power-Off Procedure ...................................................................................................... 15 7.2.1 Voltage Ramp and Device Initialization ........................................................................................................................ 15 7.2.2 Reset Initialization with Stable Power .......................................................................................................................... 17 7.2.3 Power-off Sequence .................................................................................................................................................... 17 7.2.4 Uncontrolled Power-Off Sequence .............................................................................................................................. 18 7.3 Mode Register Definition .............................................................................................................................................. 19 7.3.1 MR0 Register Information (MA 5:0 = 00 ) .................................................................................................................. 20 H 7.3.2 MR1 Register Information (MA 5:0 = 01 ) .................................................................................................................. 21 H 7.3.3 MR2 Register Information (MA 5:0 = 02 ) .................................................................................................................. 23 H 7.3.4 MR3 Register Information (MA 5:0 = 03 ) .................................................................................................................. 24 H 7.3.5 MR4 Register Information (MA 5:0 = 04 ) .................................................................................................................. 25 H 7.3.6 MR5 Register Information (MA 5:0 = 05 ) .................................................................................................................. 26 H 7.3.7 MR6 Register Information (MA 5:0 = 06 ) .................................................................................................................. 26 H 7.3.8 MR7 Register Information (MA 5:0 = 07 ) .................................................................................................................. 26 H 7.3.9 MR8 Register Information (MA 5:0 = 08 ) .................................................................................................................. 26 H 7.3.10 MR9 Register Information (MA 5:0 = 09 ) .................................................................................................................. 26 H 7.3.11 MR10 Register Information (MA 5:0 = 0A ) ............................................................................................................... 26 H 7.3.12 MR11 Register Information (MA 5:0 = 0B ) ............................................................................................................... 27 H 7.3.13 MR12 Register Information (MA 5:0 = 0C ) ............................................................................................................... 27 H 7.3.14 MR13 Register Information (MA 5:0 = 0D ) ............................................................................................................... 29 H 7.3.15 MR14 Register Information (MA 5:0 = 0E ) ............................................................................................................... 30 H 7.3.16 MR15 Register Information (MA 5:0 = 0F ) ................................................................................................................ 32 H 7.3.17 MR16 Register Information (MA 5:0 = 10 ) ................................................................................................................ 33 H 7.3.18 MR17 Register Information (MA 5:0 = 11 ) ................................................................................................................ 33 H 7.3.19 MR18 Register Information (MA 5:0 = 12 ) ................................................................................................................ 34 H 7.3.20 MR19 Register Information (MA 5:0 = 13 ) ................................................................................................................ 34 H 7.3.21 MR20 Register Information (MA 5:0 = 14 ) ............................................................................................................... 34 H 7.3.22 MR21 Register (Reserved) (MA 5:0 = 15 ) ................................................................................................................ 34 H 7.3.23 MR22 Register Information (MA 5:0 = 16 ) ................................................................................................................ 35 H 7.3.24 MR23 Register Information (MA 5:0 = 17 ) ................................................................................................................ 36 H 7.3.25 MR24 Register Information (MA 5:0 = 18 ) ................................................................................................................ 36 H 7.3.26 MR25 Register Information (MA 5:0 = 19 ) ................................................................................................................ 37 H 7.3.27 MR26~29 (Reserved) (MA 5:0 = 1A -1D ) ................................................................................................................ 37 H H Publication Release Date: Sep. 18, 2019 Revision: A01-003 - 1 - W66BM6NB / W66CM2NQ 7.3.28 MR30 Register Information (MA 5:0 = 1E ) ............................................................................................................... 37 H 7.3.29 MR31 (Reserved) (MA 5:0 = 1F ) .............................................................................................................................. 37 H 7.3.30 MR32 Register Information (MA 5:0 = 20 ) ................................................................................................................ 37 H 7.3.31 MR33~38 (Reserved) (MA 5:0 = 21 -26 ) ................................................................................................................. 37 H H 7.3.32 MR39 Register Information (MA 5:0 = 27 ) ................................................................................................................ 38 H 7.3.33 MR40 Register Information (MA 5:0 = 28 ) ................................................................................................................ 38 H 7.4 Command Definitions and Timing Diagrams ................................................................................................................ 39 7.4.1 Activate Command ...................................................................................................................................................... 39 7.4.1.1 8-Bank Device Operation .................................................................................................................................. 39 7.4.2 Core Timing ................................................................................................................................................................. 40 7.4.3 Read and Write Access Operations ............................................................................................................................. 41 7.4.4 Read Preamble and Postamble ................................................................................................................................... 41 7.4.5 Burst Read Operation .................................................................................................................................................. 42 7.4.6 Read Timing ................................................................................................................................................................ 46 7.4.7 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ................................................................................................... 46 7.4.7.1 tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) ....................................................... 47 7.4.7.2 tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) ............................................................ 49 7.4.7.3 tRPRE Calculation for ATE (Automatic Test Equipment) ................................................................................... 51 7.4.7.4 tRPST Calculation for ATE (Automatic Test Equipment) ................................................................................... 52 7.4.8 tDQSCK Timing Table ................................................................................................................................................. 53 7.4.8.1 CK to DQS Rank to Rank variation ................................................................................................................... 53 7.4.9 Write Preamble and Postamble ................................................................................................................................... 54 7.4.10 Burst Write Operation .................................................................................................................................................. 55 7.4.11 Write Timing ................................................................................................................................................................ 58 7.4.11.1 tWPRE Calculation for ATE (Automatic Test Equipment) .................................................................................. 59 7.4.11.2 tWPST Calculation for ATE (Automatic Test Equipment) .................................................................................. 60 7.4.12 Read and Write Latencies ........................................................................................................................................... 61 7.4.13 Write and Masked Write operation DQS controls (WDQS Control) .............................................................................. 61 7.4.13.1 WDQS Control Mode 1 - Read Based Control ................................................................................................... 62 7.4.13.2 WDQS Control Mode 2 - WDQS on/off ............................................................................................................ 62 7.4.14 Postamble and Preamble merging behavior ................................................................................................................ 67 7.4.14.1 Read to Read Operation ................................................................................................................................... 67 7.4.14.2 Write to Write Operation.................................................................................................................................... 80 7.4.15 Masked Write Operation .............................................................................................................................................. 90 7.4.15.1 Masked Write Timing constraints for BL16 ........................................................................................................ 92 7.4.16 LPDDR4X Data Mask (DM) and Data Bus Inversion (DBIdc) Function ........................................................................ 94 7.4.17 Precharge Operation ................................................................................................................................................... 97 7.4.17.1 Burst Read Operation Followed by a Precharge ............................................................................................... 98 7.4.17.2 Burst Write Operation Followed by a Precharge ................................................................................................ 99 7.4.17.3 Auto-Precharge Operation ................................................................................................................................ 99 7.4.17.4 Burst Read with Auto-Precharge ..................................................................................................................... 100 7.4.17.5 Burst Write with Auto-Precharge ..................................................................................................................... 101 7.4.18 Auto-Precharge Operation ......................................................................................................................................... 102 7.4.18.1 Delay time from Write to Read with Auto-Precharge ....................................................................................... 103 7.4.19 Refresh command ..................................................................................................................................................... 107 7.4.19.1 Burst Read operation followed by Per Bank Refresh ....................................................................................... 113 7.4.20 Refresh Requirement ................................................................................................................................................ 114 7.4.21 Self Refresh Operation .............................................................................................................................................. 115 7.4.21.1 Self Refresh Entry and Exit ............................................................................................................................. 115 7.4.21.2 Power Down Entry and Exit during Self Refresh ............................................................................................. 116 7.4.21.3 Command input Timing after Power Down Exit ............................................................................................... 117 7.4.21.4 AC Timing Table ............................................................................................................................................. 118 7.4.22 MRR, MRW, MPC Command during tXSR, tRFC ...................................................................................................... 119 7.4.23 MODE REGISTER READ (MRR) .............................................................................................................................. 120 7.4.23.1 MRR after Read and Write command ............................................................................................................. 122 7.4.23.2 MRR after Power-Down Exit ........................................................................................................................... 124 Publication Release Date: Sep. 18, 2019 Revision: A01-003 - 2 -