W956D6KBKX7I

W956D6KBKX 64Mb Async./Burst/Sync./A/D MUX TABLE OF CONTENTS 1. GENERAL DESCRIPTION .......................................................................................................... 3 2. FEATURES.................................................................................................................................. 3 3. ORDERING INFORMATION ....................................................................................................... 3 4. BALL CONFIGURATION ............................................................................................................ 4 5. BALL DESCRIPTION .................................................................................................................. 5 6. BLOCK DIAGRAM ...................................................................................................................... 6 7. INSTRUCTION SET .................................................................................................................... 7 8. FUNCTIONAL DESCRIPTION .................................................................................................... 8 8.1 Power Up Initialization ..................................................................................................................... 8 8.2 Bus Operating Modes ...................................................................................................................... 8 8.3 Asynchronous Modes ...................................................................................................................... 8 8.3.1 READ Operation (ADV LOW) .................................................................................................................. 9 8.3.2 WRITE Operation (ADV LOW) ................................................................................................................ 9 8.4 Burst Mode Operation .................................................................................................................... 10 8.4.1 Burst Mode READ (4-word burst) ............................................................................................................ 10 8.4.2 Burst Mode WRITE (4-word burst) .......................................................................................................... 11 8.4.3 Refresh Collision During Variable-Latency READ Operation .................................................................. 12 8.5 Mixed-Mode Operation .................................................................................................................. 13 8.5.1 WAIT Operation ....................................................................................................................................... 13 8.5.2 Wired-OR WAIT Configuration ................................................................................................................ 13 8.5.3 LB / UB Operation ................................................................................................................................. 14 8.6 Low Power Operation .................................................................................................................... 14 8.6.1 Standby Mode Operation ......................................................................................................................... 14 8.6.2 Temperature Compensated Refresh ....................................................................................................... 14 8.6.3 Partial-Array Refresh ............................................................................................................................... 14 8.6.4 Deep Power-Down Operation .................................................................................................................. 14 8.7 Registers ....................................................................................................................................... 15 8.7.1 Access Using CRE .................................................................................................................................. 15 8.7.2 Configuration Register WRITE Asynchronous Mode Followed by READ Operation .............................. 15 8.7.3 Configuration Register WRITE Synchronous Mode Followed by READ Operation ................................ 16 8.7.4 Configuration Register READ Asynchronous Mode Followed by READ ARRAY Operation .................. 17 8.7.5 Configuration Register READ Synchronous Mode Followed by READ ARRAY Operation .................... 18 8.7.6 Software Access ...................................................................................................................................... 19 8.7.7 Load Configuration Register .................................................................................................................... 19 8.7.8 Read Configuration Register ................................................................................................................... 20 8.8 Bus Configuration Register ............................................................................................................ 20 8.8.1 Bus Configuration Register Definition ...................................................................................................... 21 8.8.2 Burst Length (BCR 2:0 ) Default = Continuous Burst .............................................................................. 22 8.8.3 Burst Wrap (BCR 3 ) Default = No Wrap ................................................................................................. 22 8.8.4 Sequence and Burst Length .................................................................................................................... 23 8.8.5 Drive Strength (BCR 5:4 ) Default = Outputs Use Half-Drive Strength ................................................... 24 8.8.6 Drive Strength .......................................................................................................................................... 24 8.8.7 WAIT Configuration. (BCR 8 ) Default =WAIT Transitions 1 Clock Before Data Valid/ Invalid ............... 24 8.8.8 WAIT Polarity (BCR 10 ) Default = WAIT Active HIGH ........................................................................... 24 8.8.9 WAIT Configuration During Burst Operation ........................................................................................... 25 8.8.10 Latency Counter (BCR 13:11 ) Default = Three Clock Latency ............................................................ 25 8.8.11 Initial Access Latency (BCR 14 ) Default = Variable ............................................................................. 25 8.8.12 Allowed Latency Counter Settings in Variable Latency Mode ............................................................... 25 8.8.13 Latency Counter (Variable Initial Latency, No Refresh Collision) ......................................................... 26 8.8.14 Allowed Latency Counter Settings in Fixed Latency Mode ................................................................... 26 8.8.15 Latency Counter (Fixed Latency) .......................................................................................................... 27 8.8.16 Operating Mode (BCR 15 ) Default is Asynchronous Operation ........................................................... 27 Publication Release Date: Mar. 02, 2017 Revision: A01-001 - 1 - W956D6KBKX 8.9 Refresh Configuration Register ...................................................................................................... 28 8.9.1 Refresh Configuration Register Mapping ................................................................................................ 28 8.9.2 Partial Array Refresh (RCR 2:0 ) Default = Full Array Refresh ............................................................... 28 8.9.3 Address Patterns for PAR (RCR 4 = 1) ................................................................................................. 29 8.9.4 Deep Power-Down (RCR 4 ) Default = DPD Disabled ............................................................................ 29 8.10 Device Identification Register ....................................................................................................... 29 9. ELECTRICAL CHARACTERISTIC ........................................................................................... 30 9.1 Absolute Maximum DC, AC Ratings .............................................................................................. 30 9.2 Electrical Characteristics and Operating Conditions ....................................................................... 30 9.3 Deep Power-Down Specifications .................................................................................................. 31 9.4 Partial Array Self Refresh Standby Current .................................................................................... 31 9.5 Capacitance ................................................................................................................................... 31 9.6 AC Input-Output Reference Waveform ........................................................................................... 31 9.7 AC Output Load Circuit .................................................................................................................. 31 10. TIMING REQUIREMENTS....................................................................................................... 32 10.1 Read, Write Timing Requirements ............................................................................................... 32 10.1.1 Asynchronous READ Cycle Timing Requirements ............................................................................... 32 10.1.2 Burst READ Cycle Timing Requirements .............................................................................................. 33 10.1.3 Asynchronous WRITE Cycle Timing Requirements .............................................................................. 34 10.1.4 Burst WRITE Cycle Timing Requirements ............................................................................................ 35 10.2 TIMING DIAGRAMS .................................................................................................................... 36 10.2.1 Initialization Period ................................................................................................................................. 36 10.2.2 DPD Entry and Exit Timing Parameters ................................................................................................ 36 10.2.3 Initialization Timing Parameters ............................................................................................................ 36 10.2.4 Initialization and DPD Timing Parameters ............................................................................................. 36 10.2.5 Asynchronous READ ............................................................................................................................. 37 10.2.6 Single Access Burst READ Operation - Variable Latency..................................................................... 38 10.2.7 Four Word Burst READ Operation-Variable Latency ............................................................................ 39 10.2.8 Single-Access Burst READ Operation-Fixed Latency ........................................................................... 40 10.2.9 Four Word Burst READ Operation-Fixed Latency ................................................................................. 41 10.2.10 Burst READ Terminate at End-of-Row (Wrap Off) .............................................................................. 42 10.2.11 Burst READ Row Boundary Crossing ................................................................................................. 43 10.2.12 Asynchronous WRITE ......................................................................................................................... 44 10.2.13 Burst WRITE Operation-Variable Latency Mode ................................................................................. 45 10.2.14 Burst WRITE Operation-Fixed Latency Mode ..................................................................................... 46 10.2.15 Burst WRITE Terminate at End of Row (Wrap Off) ............................................................................. 47 10.2.16 Burst WRITE Row Boundary Crossing ................................................................................................ 48 10.2.17 Burst WRITE Followed by Burst READ ............................................................................................... 49 10.2.18 Asynchronous WRITE Followed by Burst READ ................................................................................ 50 10.2.19 Burst READ Followed by Asynchronous WRITE ................................................................................ 51 10.2.20 Asynchronous WRITE Followed by Asynchronous READ .................................................................. 52 11. PACKAGE SPECIFICATION .................................................................................................. 53 12. REVISION HISTORY ............................................................................................................... 54 Publication Release Date: Mar. 02, 2017 Revision: A01-001 - 2 -