ESD7002, SZESD7002 ESD Protection Diode Low Capacitance ESD Protection Diode for High Speed Data Line The ESD7002 surge protection device is designed to protect high www.onsemi.com speed data lines from ESD. Ultralow capacitance and low ESD clamping voltage make this device an ideal solution for protecting MARKING voltage sensitive high speed data lines. The flowthrough style DIAGRAM package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed SC70 differential lines such as USB 3.0 and HDMI. 72 M CASE 419 STYLE 4 Features 1 Low Capacitance (0.3 pF Typical, I/O to GND) 72 = Specific Device Code Diode capacitance matching M = Date Code Protection for the Following IEC Standards: = PbFree Package (Note: Microdot may be in either location) IEC 6100042 (Level 4) Low ESD Clamping Voltage PIN CONFIGURATION SZ Prefix for Automotive and Other Applications Requiring Unique AND SCHEMATIC Site and Control Change Requirements AECQ101 Qualified and PPAP Capable Pin 1 Pin 2 These Devices are PbFree and are RoHS Compliant Typical Applications USB2.0/3.0 LVDS HDMI Pin 3 High Speed Differential Pairs MAXIMUM RATINGS (T = 25C unless otherwise noted) J = Rating Symbol Value Unit Operating Junction Temperature Range T 55 to +125 C J Storage Temperature Range T 55 to +150 C stg Lead Solder Temperature T 260 C L ORDERING INFORMATION Maximum (10 Seconds) See detailed ordering, marking and shipping information in the IEC 6100042 Contact (ESD) ESD 8 kV package dimensions section on page 5 of this data sheet. IEC 6100042 Air (ESD) ESD 15 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: July, 2017 Rev. 4 ESD7002/DESD7002, SZESD7002 ELECTRICAL CHARACTERISTICS (T = 25C unless otherwise specified) A Parameter Symbol Conditions Min Typ Max Unit Reverse Working V I/O Pin to GND 16 V RWM Voltage Breakdown Voltage V I = 1 mA, I/O Pin to GND 16.5 23 V BR T Reverse Leakage I V = 5 V, I/O Pin to GND 1 A R RWM Current Clamping Voltage V IEC6100042, 8 kV Contact See Figures 3 and 4 C (Note 1) Clamping Voltage TLP V I = 8 A 31.2 V C PP (Note 2) I = 16 A 33.9 PP I = 8 A 5.5 PP I = 16 A 10.8 PP Junction Capacitance C VR = 0 V, f = 1 MHz between I/O1 to GND and I/O 5 10 % J Match 2 to GND Junction Capacitance C VR = 0 V, f = 1 MHz between I/O Pins 0.2 0.4 pF J Junction Capacitance C VR = 0 V, f = 1 MHz between I/O Pins and GND 0.3 0.5 pF J 3dB Bandwidth f R = 50 5 GHz BW L 1. For test procedure see Figures 5 and 6 and application note AND8307/D. 2. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z = 50 , t = 100 ns, t = 4 ns, averaging window t = 30 ns to t = 60 ns. 0 p r 1 2 1.0 1E02 1E03 0.9 1E04 0.8 1E05 0.7 1E06 0.6 1E07 0.5 1E08 0.4 1E09 0.3 1E10 0.2 1E11 0.1 1E12 0 1E13 0 2 46 8 10 12 14 16 18 20 2224 02 4 6 8 10 12 14 VOLTAGE (V) VBias (V) Figure 1. Typical IV Characteristic Curve Figure 2. Typical CV Characteristic Curve 150 10 140 0 130 10 120 20 110 30 100 40 90 50 80 60 70 70 60 80 50 90 40 100 30 110 20 120 10 130 0 140 10 150 50 0 50 100 150 200 250 300 350 400 20 0 20 40 60 80 100 120 140 160 180 200 TIME (ns) TIME (ns) Figure 3. IEC6100042 +8 kV Contact ESD Figure 4. IEC6100042 8 kV Contact ESD Clamping Voltage Clamping Voltage www.onsemi.com 2 VOLTAGE (V) CURRENT (A) VOLTAGE (V) CAPACITANCE (pF)