Product Information

PE43204MLIBA

PE43204MLIBA electronic component of pSemi

Datasheet
Digital Attenuator 18dB Attenuation 3GHz 12-Pin QFN EP T/R
Manufacturer: pSemi
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

27: USD 2.5394 ea
Line Total: USD 68.56

0 - Global Stock
MOQ: 27  Multiples: 1
Pack Size: 1

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0 - WHS 1


Ships to you between Wed. 22 May to Tue. 28 May

MOQ : 27
Multiples : 1
27 : USD 2.5394

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Additional Infomation About Product

Product Specification PE43204 50 RF Digital Attenuator 2-bit 0, 6, 12, and 18 dB States Product Description Features The PE43204 is a 50 , HaRP-enhanced, high linearity, 2-bit HaRP-enhanced UltraCMOS device RF Digital Step Attenuator (DSA) covering an 18 dB attenuation range in 6 dB steps. With a parallel control Fast switching speed: Typical 26 ns interface, it maintains high attenuation accuracy, fast switching High Linearity: Typical +61 dBm IP3 speed, low insertion loss and low power consumption. This next generation Peregrine DSA is available in a 3x3 mm 12- Small -Error lead QFN footprint. Best in class 2000 V HBM ESD tolerance Attenuation: 6, 12, and 18 dB States The PE43204 is manufactured on Peregrines UltraCMOS process, a patented variation of silicon-on-insulator (SOI) Parallel Control technology on a sapphire substrate, offering the performance CMOS Compatible of GaAs with the economy and integration of conventional CMOS. Packaged in a 12-lead 3x3x0.85 mm QFN Figure 1. Package Type 12-lead 3x3x0.85 mm QFN Package Figure 2. Functional Schematic Diagram Switched Attenuator Array RF Input RF Output 2 Parallel Control Control Logic Interface Document No. 70-0257-03 www.psemi.com 2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE43204 Product Specification Table 1. Electrical Specifications +25C, V = 3.3 V DD Parameter Test Conditions Min Typical Max Units Frequency Range 50 - 3000 MHz Attenuation Range 6 dB,12 dB and 18 dB steps 0 -18 dB Insertion Loss 0.6 0.7 dB 0 dB - 18 dB Attenuation Settings Attenuation Error 50 MHz to < 2000 MHz +0.1 -0.25 / + 0.40 dB 2000 MHz 3000 MHz +0.2 -0.10 / +0.50 dB Return Loss 15 dB Relative Phase All States 11 deg P1dB Input +28 +30 dBm IIP3 IIP3 Two tones at +18 dBm, 20 MHz spacing +61 dBm Switching Speed 50% DC CTRL to 10% / 90% RF 26 ns Performance Plots Figure 3. Attenuation vs. Attenuation Setting Figure 4. Attenuation Error vs. Frequency T = +25C 6dB State 12dB State 18dB State 0.50 18 0.40 0.30 12 0.20 0.10 6 0.00 -0.10 0 0 500 1000 1500 2000 2500 3000 3500 4000 0 6 12 18 Frequency (MHz.) Attenuation State (dB.) Note: Attenuation Error Equation - AE = ABS ABS(Insertion Loss Attenuation Setting) - ABS(Reference Loss) - ABS(Attenuation Setting) Figure 5. Insertion Loss vs. Temperature Figure 6. Input Return Loss vs Attenuation T = +25C +25C -40C +85C 0dB 6dB 12dB 18dB 0.00 0.00 -0.10 -5.00 -0.20 -10.00 -0.30 -15.00 -0.40 -0.50 -20.00 -0.60 -25.00 -0.70 -30.00 -0.80 -35.00 -0.90 -40.00 -1.00 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (MHz.) Frequency (MHz) 2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0257-03 UltraCMOS RFIC Solutions Page 2 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents:

HS Compliance

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:

Psemi may also be referenced as

Peregrine
PEREGRINE SEMICONDUCTOR

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