Product Specification PE64904 UltraCMOS Digitally Tunable Capacitor (DTC) 100 - 3000 MHz Product Description Features The PE64904 is a DuNE-enhanced Digitally Tunable Capacitor (DTC) based on Peregrines UltraCMOS 3-wire (SPI compatible) Serial Interface technology. DTC products provide a monolithically with built-in bias voltage generation and integrated impedance tuning solution for demanding RF ESD protection applications. DuNE-enhanced UltraCMOS device 5-bit 32-state Digitally Tunable Capacitor The PE64904 offers high RF power handling and ruggedness, while meeting challenging harmonic and Series configuration C = 0.60 - 4.60 pF linearity requirements. (7.7:1 tuning ratio) in discrete 129 fF steps Shunt configuration C = 1.14 - 5.10 pF This highly versatile product can be used in series or shunt (4.6:1 tuning ratio) in discrete 129 fF steps configurations to support a wide variety of tuning circuit High RF Power Handling (up to 38 dBm, topologies. 30 V RF) and High Linearity pk Wide power supply range (2.3 to 3.6V) The device is controlled through the widely supported and low current consumption 3-wire (SPI compatible) interface. All decoding and biasing (typ. 140 A at 2.6V) is integrated on-chip and no external bypassing or filtering components are required. Excellent 1.5 kV HBM ESD tolerance on all pins Peregrines DuNE technology enables excellent linearity 2 x 2 x 0.45 mm QFN package and exceptional harmonic performance. DuNE devices Applications include: deliver performance superior to GaAs devices with the Tunable Filter Networks economy and integration of conventional CMOS. Tunable Antennas RFID Tunable Matching Networks Phase Shifters Figure 1. Functional Block Diagram Wireless Communications Figure 2. Package Type 10L 2 x 2 x 0.45 mm QFN package RF- RF+ ESD ESD CMOS Control Serial Interface Driver and ESD 71-0066-01 DOC-87399-1 2018 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE64904 Product Specification Table 1. Electrical Specifications 25C, V = 2.6V DD Parameter Configuration Condition Min Typ Max Units Operating Frequency Range Both 100 3000 MHz Series State = 00000, 100 MHz (RF+ to RF-) 0.49 0.60 0.71 Minimum Capacitance pF Shunt State = 00000, 100 MHz (RF+ to Grounded RF-) 0.90 1.10 1.30 Series State = 11111, 100 MHz (RF+ to RF-) 3.78 4.60 5.45 Maximum Capacitance pF Shunt State = 11111, 100 MHz (RF+ to Grounded RF-) 4.19 5.10 6.00 Parasitic Capacitance Series All States, 100 MHz (RF+ to GND, RF- to GND) 0.5 pF Series 100 MHz 7.7:1 Tuning Ratio Shunt 100 MHz 4.6:1 Step Size Both 5 bits (32 states), constant step size (100 MHz) 0.129 pF State = 00000 1.40 Equivalent Series Resistance Series State = 11111 1.33 100 MHz, with L removed 10 s 1 GHz, with L removed 35 1 s Quality Factor (C ) Shunt min 2 GHz, with L removed 32 s 3 GHz, with L removed 25 s 100 MHz, with L removed 27 s 1 GHz, with L removed 25 1 s Quality Factor (C ) Shunt max 2 GHz, with L removed 11 s 3 GHz, with L removed 6 s State 00000 7.5 Self Resonant Frequency Shunt GHz State 11111 3.1 2 Harmonics (2fo) 100 MHz - 3 GHz -36 dBm Series 2 Harmonics (3fo) 100 MHz - 3 GHz -36 dBm Input Intercept Point (2nd Order) Series 100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing 105 dBm Input Intercept Point (3rd Order) Series 100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing 65 dBm 50% CTRL to 10/90% delta capacitance between any two 3, 4 Switching Time Both 12 s states Time from V within specification to all performances within 3 DD Start-up Time Both 100 s specification State change from standby mode to RF state to all perfor- 3, 4 Wake-up Time Both 100 s mances within specification Notes: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit. Q = X /R = (X-X )/R, where X = X +X , X = 2*pi*f*L, X = -1/(2*pi*f*C), which is equal to removing the effect of parasitic inductance L C L L C L C S. 2. In series or shunt between 50 ports. Pulsed RF input with 4620 s period, 50% duty cycle, measured per 3GPP TS 45.005. 3. DC path to ground at RF+ and RF- must be provided to achieve specified performance. 4. State change activated on falling edge of SEN following data word. 2018 Peregrine Semiconductor Corp. All rights reserved. DOC-87399-1 Page 2 of 11