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AS4C128M16D3LB-12BIN

AS4C128M16D3LB-12BIN electronic component of Alliance Memory

Datasheet
DRAM 2G 1.35V 800MHz 128Mx16 DDR3 I-Temp
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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N/A

Obsolete

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0 - WHS 1

MOQ : 190
Multiples : 190

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AS4C128M16D3LB-12BIN
Alliance Memory

190 : USD 6.1643
570 : USD 5.8503
1140 : USD 5.5944
N/A

Obsolete

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Additional Infomation About Product

AS4C128M16D3LB-12BIN Revision History 2G DDR3L AS4C128M16D3LB-12BIN 96ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Dec. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 86 - Rev.1.0 Dec. 2017AS4C128M16D3LB-12BIN 128M x 16 bit DDR3L Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Dec. /2017) Features Overview JEDEC Standard Compliant The 2Gb Double-Data-Rate-3L (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.35V (1.283V ~ 1.45V) DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = +1.5V 0.075V DD DDQ DRAM. Operating temperature: T = -40~95 C (Industrial) C The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank Supports JEDEC clock jitter specification devices. These synchronous devices achieve high speed Fully synchronous operation double-data-rate transfer rates of up to 1600 Mb/sec/pin Fast clock rate: 800MHz for general applications. Differential Clock, CK & CK The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address Bidirectional differential data strobe inputs are synchronized with a pair of externally supplied - DQS & DQS differential clocks. Inputs are latched at the cross point 8 internal banks for concurrent operation of differential clocks (CK rising and CK falling). All I/Os 8n-bit prefetch architecture are synchronized with differential DQS pair in a source Pipelined internal architecture synchronous fashion. Precharge & active power down These devices operate with a single 1.35V -0.067V / Programmable Mode & Extended Mode registers +0.1V power supply. Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 9 x 13 x 1.2mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Org Max Clock (MHz) Product part No Package 800 AS4C128M16D3LB-12BIN Industrial -40C to 95C 96-ball FBGA 128M x 16 Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 800 MHz 11 DDR3 L-1600 Confidential - 2 of 86 - Rev.1.0 Dec. 2017

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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