AS4C16M16S 16M x 16 bit Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 1.4, Feb. /2012) Overview Features he 256Mb SDRAM is a high-speed CMOS T Fast access time from clock: 5.4/5.4 ns synchronous DRAM containing 256 Mbits. It is Fast clock rate: 166/143 MHz internally configured as 4 Banks of 4M word x 16 Fully synchronous operation DRAM with a synchronous interface (all signals are Internal pipelined architecture registered on the positive edge of the clock signal, 4M word x 16-bit x 4-bank CLK). Read and write accesses to the SDRAM are Programmable Mode registers burst oriented accesses start at a selected location and continue for a programmed number of locations in - CAS Latency: 2, or 3 a programmed sequence. Accesses begin with the - Burst Length: 1, 2, 4, 8, or full page registration of a BankActivate command which is then - Burst Type: Sequential or Interleaved followed by a Read or Write command. - Burst stop function The SDRAM provides for programmable Read or Auto Refresh and Self Refresh Write burst lengths of 1, 2, 4, 8, or full page, with a 8192 refresh cycles/64ms burst termination option. An auto precharge function CKE power down mode may be enabled to provide a self-timed row precharge Single +3.3V power supply that is initiated at the end of the burst sequence. The Interface: LVTTL refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the Operating temperature range system can choose the most suitable modes to - Commercial (0 ~ 70C) maximize its performance. These devices are well - Industrial (-40 ~ 85C) suited for applications requiring high memory - Automotive (-40 ~ 105C) bandwidth and particularly well suited to high 54-pin 400 mil plastic TSOP II package performance PC applications. 54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package All parts fully ROHS Compliant Table 1. Key Specifications AS4C16M16S -6/7 tCK3 Clock Cycle time (min.) 6/7 ns tAC3 Access time from CLK (max.) 5.4/5.4 ns tRAS Row Active time (min.) 42/49 ns tRC Row Cycle time (min.) 60/63 ns Table 2. Ordering Information Part Number Frequency Package AS4C16M16S-7TCN 143 MHz 54 pin TSOP II AS4C16M16S-6TCN 166 MHz 54 pin TSOP II AS4C16M16S-6TIN 166 MHz 54 pin TSOP II AS4C16M16S-6BIN 166 MHz 54 ball TFBGA AS4C16M16S-7BCN 143 MHz 54 ball TFBGA AS4C16M16S-6TAN 166 MHz 54 pin TSOP II T : indicates TSOP II package B : indicates TFBGA package N : indicates Pb free and Halogen free ROHS compliant parts C: Commercial I: Industrial A: Automotive temperatures Confidential 1 Rev 3 Feb. 2014 AS4C16M16S Figure 1.1 Ball Assignment (Top View) Figure 1. Pin Assignment (Top View) VDD 1 54 VSS 1 2 3 7 8 9 DQ0 2 53 DQ15 3 52 VDDQ VSSQ VSS DQ15 VSSQ VDDQ DQ0 VDD A DQ1 4 51 DQ14 DQ2 5 50 DQ13 DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 B VSSQ 6 49 VDDQ DQ3 7 48 DQ12 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 C 8 47 DQ4 DQ11 VDDQ 9 46 VSSQ DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 D DQ5 10 45 DQ10 DQ6 11 44 DQ9 DQ8 NC VSS VDD LDQM DQ7 E VSSQ 12 43 VDDQ 13 42 DQ7 DQ8 UDQM CLK CKE CAS RAS WE F VDD 14 41 VSS LDQM 15 40 NC A12 A11 A9 BA0 BA1 CS G WE 16 39 UDQM CAS 17 38 CLK A 8 A7 A6 A 0 A1 A10 H RAS 18 37 CKE CS 19 36 A12 VSS A5 A4 A3 A2 VDD J BA0 20 35 A11 BA1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 VDD 27 28 VSS Confidential 2 Rev. 3 Feb. /2014