AS4C16M16SA-C&I Revision History Revision Details Date Rev 1.0 Preliminary datasheet February 2014 Rev 2.0 Correct some typing mistakes. March 2014 Rev 3.0 1. Add AS4C16M16SA-6TCN part. March 2015 2. Modify ordering information. 3. Add part number system on the last page. Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. Confidential 0 Rev. 3.0 Mar./2015 AS4C16M16SA-C&I 256M (16Mx16bit) Synchronous DRAM (SDRAM) Confidential Advanced(Rev. 3.0, Mar. /2015) Features Overview Fast access time from clock: 5/5.4 ns The 256Mb SDRAM is a high-speed CMOS Fast clock rate: 166/143 MHz synchronous DRAM containing 256 Mbits. It is internally configured as 4 Banks of 4M word x 16 Fully synchronous operation DRAM with a synchronous interface (all signals are Internal pipelined architecture registered on the positive edge of the clock signal, 4M word x 16-bit x 4-bank CLK). Read and write accesses to the SDRAM are Programmable Mode registers burst oriented accesses start at a selected location - CAS Latency: 2 or 3 and continue for a programmed number of locations in - Burst Length: 1, 2, 4, 8, or full page a programmed sequence. Accesses begin with the - Burst Type: Sequential or Interleaved registration of a BankActivate command which is then followed by a Read or Write command. - Burst stop function Operating temperature range The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a - Commercial (0 ~ 70C) burst termination option. An auto precharge function - Industrial (-40 ~ 85C) may be enabled to provide a self-timed row precharge Auto Refresh and Self Refresh that is initiated at the end of the burst sequence. The 8192 refresh cycles/64ms refresh functions, either Auto or Self Refresh are easy CKE power down mode to use. Single +3.3V 0.3V power supply By having a programmable mode register, the system Interface: LVTTL can choose the most suitable modes to maximize its 54-pin 400 mil plastic TSOP II package performance. These devices are well suited for applications requiring high memory bandwidth and 54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package particularly well suited to high performance PC - All parts ROHS are compliant applications. Table 1. Key Specifications AS4C16M16SA -6/7 tCK3 Clock Cycle time (min.) 6/7 ns tAC3 Access time from CLK (max.) 5/5.4 ns tRAS Row Active time (min.) 42/42 ns tRC Row Cycle time (min.) 60/63 ns Table 2. Ordering Information Temperature Temp Range Part Number Frequency Package Commercial 0~70 AS4C16M16SA-7TCN 143 MHz 54 pin TSOP II Commercial 0~70 AS4C16M16SA-6TCN 166 MHz 54 pin TSOP II AS4C16M16SA-6TIN 166 MHz 54 pin TSOP II Industrial -40~85 Commercial AS4C16M16SA-7BCN 143 MHz 54 ball TFBGA 0~70 AS4C16M16SA-6BIN 166 MHz 54 ball TFBGA Industrial -40~85 T : indicates TSOP II package B : indicates TFBGA package C: Commercial I: Industrial N : indicates Pb free and Halogen free Confidential 1 Rev. 3.0 Mar. /2015