AS4C16M32MD1 512M (16M x32 bit) Mobile DDR SDRAM Confidential (Rev. 1.0, July. /2014) LPDDR MEMORY 512M (16Mx32bit) Mobile DDR SDRAM Revision History Revision No Description Date 1.0 Initial Release 2014/07/18 AS4C16M32MD1 512M (16M x32 bit) LP Mobile DDR SDRAM Confidential (Rev. 1.0, July. /2014) 1. FEATURES Density : 512Mbit Low power consumption Partial Array Self-Refresh (PASR) Data width: x32 Auto Temperature Compensated Self-Refresh Power supply : VDD, VDDQ = 1.7 to 1.95V (ATCSR) by built-in temperature sensor Speed Deep power down mode(DPD Mode) - Clock frequency : 200MHz (max.) Burst termination by burst stop command and - Data rate : 400Mbps (max.) precharge command Four internal banks for concurrent DDL is not implemented operation Interface : LVCMOS Double-data-rate architecture : Two data transfers per one clock cycle Burst lengths (BL) : 2, 4, 8, 16 The high speed data transfer is realized by the Burst type (BT) - Sequential : 2, 4, 8, 16 2bits prefetch pipelined architecture Bi-directional data strobe (DQS) is transmitted/ - Interleave : 2, 4, 8, 16 CAS latency (CL) : 3 received with data for capturing data at the receiver Precharge : auto precharge option for each burst access DQS is edge-aligned with data for READs center-aligned with data for WRITEs Driver strength : normal, 1/2, 1/4, 1/8 Differential clock inputs (CK and CK ) Refresh : auto-refresh, self-refresh Refresh cycles : 8192 cycles/64ms Commands entered on each positive CK edge data and data mask referenced to both edges - Average refresh period : 7.8us of DQS Operating temperature range - Commercial (Extended) -25C to +85C Data mask (DM) for write data - Industrial -40C to +85C Clock Stop capability during idle periods Package: 90-ball FPBGA (8x13.0mm) All parts are ROHS Compliant Confidential 2 Rev. 1.0/July 2014