4Gb Auto-AS4C256M16D3 Revision History 4Gb Auto-AS4C256M16D3 - 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet June 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -1/83- Rev.1.0 June 20154Gb Auto-AS4C256M16D3 Features Overview The 4Gb Double-Data-Rate-3 DRAMs is double JEDEC Standard Compliant data rate architecture to achieve high-speed operation. Power supplies: V & V = +1.5V 0.075V DD DDQ It is internally configured as an eight bank DRAM. Operating temperature: -40~105C (TC) The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 AEC-Q100 compliant bank devices. These synchronous devices achieve high Supports JEDEC clock jitter specification speed double-data-rate transfer rates of up to 1600 Mb/ Fully synchronous operation sec/pin for general applications. Fast clock rate: 667/800MHz The chip is designed to comply with all key DDR3 Differential Clock, CK & CK DRAM key features and all of the control and address Bidirectional differential data strobe inputs are synchronized with a pair of externally supplied - DQS & DQS differential clocks. Inputs are latched at the cross point of 8 internal banks for concurrent operation differential clocks (CK rising and CK falling). All I/Os are 8n-bit prefetch architecture synchronized with differential DQS pair in a source synchronous fashion. Pipelined internal architecture Precharge & active power down These devices operate with a single 1.5V 0.075V power supply and are available in BGA Programmable Mode & Extended Mode registers packages. Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s -40C TC +85C 3.9s +85C TC +105C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 9 x 13 x 1.2mm FBGA package - Pb and Halogen Free Table 1. Speed Grade Information Speed Grade Clock Frequency CAS Latency t t (ns) (ns) RCD RP 13.75 13.75 DDR3-1600 800 MHz 5 Table 2. Ordering Information Org Temperature Max Clock (MHz) Product part No Package 800 AS4C256M16D3-12BAN 256M x 16 Automotive -40C to 105C 96-ball FBGA Confidential -2/83- Rev.1.0 June 2015