Product Information

AS4C256M16D3B-12BAN

AS4C256M16D3B-12BAN electronic component of Alliance Memory

Datasheet
DRAM 4G 1.5V 800MHz 256Mx16 DDR3 A-Temp
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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N/A

Obsolete

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0 - WHS 1

MOQ : 1
Multiples : 1

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AS4C256M16D3B-12BAN
Alliance Memory

1 : USD 12.4342
10 : USD 11.0515
25 : USD 11.0515
50 : USD 11.0515
100 : USD 10.1861
250 : USD 10.017
500 : USD 9.6887
1000 : USD 9.639
2000 : USD 9.639
N/A

Obsolete

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RoHS - XON
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Additional Infomation About Product

AS4C256M16D3B-12BAN Revision History 4Gb AS4C256M16D3B - 12BAN 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet May. 2018 Rev 1.2 Added in previously omitted data - Page 2 April 2019 -JEDEC Standard Compliant -AEC-Q100 Compliant Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/41 - Rev.1.2 April 2019AS4C256M16D3B-12BAN Specifications Features - JEDEC Standard Compliant - Double-data-rate architecture two data transfers per clock - AEC-Q100 Compliant cycle - Density : 4G bits - The high-speed data transfer is realized by the 8 bits - Organization : 32M words x 16 bits x 8 banks prefetch pipelined architecture - Package : - Bi-directional differential data strobe (DQS and DQS) is - 96-ball FBGA transmitted/received with data for capturing data at the re- - Lead-free (RoHS compliant) and Halogen-free ceiver - Power supply : VDD, VDDQ = 1.5V 0.075V - DQS is edge-aligned with data for READs center-aligned - Data rate : with data for WRITEs - 1600Mbps - Differential clock inputs (CK and CK) - 2KB page size - DLL aligns DQ and DQS transitions with CK transitions - Row address: A0 to A14 - Commands entered on each positive CK edge data and - Column address: A0 to A9 data mask referenced to both edges of DQS - Eight internal banks for concurrent operation - Data mask (DM) for write data - Burst lengths (BL) : 8 and 4 with Burst Chop (BC) - Burst type (BT) : - Posted CAS by programmable additive latency for better - Sequential (8, 4 with BC) command and data bus efficiency - Interleave (8, 4 with BC) - On-Die Termination (ODT) for better signal quality - CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11 - Synchronous ODT - CAS Write Latency (CWL) : 5, 6, 7, 8 - Dynamic ODT - Precharge : auto precharge option for each burst access - Asynchronous ODT - Driver strength : RZQ/7, RZQ/6 (RZQ = 240 ) - Multi Purpose Register (MPR) for pre-defined pattern read - Refresh : auto-refresh, self-refresh out - Refresh cycles : - Average refresh period - ZQ calibration for DQ drive and ODT 7.8 s at -40C Tc +85C - Programmable Partial Array Self-Refresh (PASR) 3.9 s at +85C < Tc +95C - RESET pin for Power-up sequence and reset function - SRT range : Normal/extended - Operating case temperature range - Programmable Output driver impedance control - Automotive Tc = -40C to +105C Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package AS4C256M16D3B-12BAN 256Mx16 800 96-ball FBGA Automotive -40C to +105C Table 2. Speed Grade Information Speed Grade CAS Latency tRCD (ns) Clock Frequency tRP (ns) DDR3-1600 800MHz 11 13.75 13.75 Confidential - 2/41 - Rev.1.2 April 2019

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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