AS4C256M16D3LC Revision History 4Gb AS4C256M16D3 LC Automotive 96 ball FBGA Package Date Revision Rev 1.0 Initial Release Sept.2020 ALLIANCE MEMORY, Inc. reserves the right to change products or specification without notice. 12815 NE 124th Street Suite D, Kirkland, WA 98034 USA Main +1(425)868-4456 Fax:+1 (425)898-8628 Confidential - 1 of 89 - Rev.1.0. Sep. 2020AS4C256M16D3LC 256M x 16 bit DDR3L Synchronous DRAM (SDRAM) Automotive (Rev. 1.0, Sep. /2020) Features Overview JEDEC Standard Compliant The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed AEC-Q100 Compliant operation. It is internally configured as an eight bank Power supplies: V & V = +1.35V DD DDQ DRAM. Backward compatible to V & V = +1.5V 0.075V DD DDQ The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank Operating temperature: T = -40~105 C (Automotive) C devices. These synchronous devices achieve high speed Supports JEDEC clock jitter specification double-data-rate transfer rates of up to 1866 Mb/sec/pin Fully synchronous operation for general applications. The chip is designed to comply with all key DDR3L Fast clock rate: 800/933MHz DRAM key features and all of the control and address Differential Clock, CK & CK inputs are synchronized with a pair of externally supplied Bidirectional differential data strobe differential clocks. Inputs are latched at the cross point - DQS & DQS of differential clocks (CK rising and CK falling). All I/Os 8 internal banks for concurrent operation are synchronized with differential DQS pair in a source 8n-bit prefetch architecture synchronous fashion. Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Auto Refresh and Self Refresh - Not Support self refresh function with T > 95C C Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C - 8192 cycles/16ms (1.95us at +95C T +105C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant 96-ball 7.5 x 13.5 x 1.2mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Org Temperature Product part No Max Clock (MHz) Package 933 256M x 16 Automotive -40C to 105C 96-ball FBGA AS4C 256M 16D3 L C-1 0B AN 800 96-ball FBGA 256M x 16 Automotive -40C to 105C AS4C 256M 16D3 L C-1 2B AN Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t t (ns) (ns) RP RCD 13 933MHZ DDR3 L-1 866 13.91 13.91 800MHZ 11 13.75 DDR3 L-1600 13.75 Confidential - 2 of 89 - Rev.1.0. Sep. 2020