Product Information

AS4C256M8D2A-25BCN

AS4C256M8D2A-25BCN electronic component of Alliance Memory

Datasheet
DRAM 2Gb, 1.8V, 400Mhz 256M x 8 DDR2
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 16.3427 ea
Line Total: USD 16.34

236 - Global Stock
Ships to you between
Tue. 28 May to Thu. 30 May
MOQ: 1  Multiples: 1
Pack Size: 1

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156 - WHS 1


Ships to you between Tue. 28 May to Thu. 30 May

MOQ : 1
Multiples : 1

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AS4C256M8D2A-25BCN
Alliance Memory

1 : USD 13.524
10 : USD 12.7305
25 : USD 11.1665
100 : USD 11.017
264 : USD 10.6145
528 : USD 10.5455
1056 : USD 10.5455
2640 : USD 10.5455
5016 : USD 10.4995

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Additional Infomation About Product

2Gb DDR2 - AS4C256M8D2 Revision History 2Gb DDR2 -AS4C256M8D2 - 60 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet September 2014 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -1/70- Rev.1.0 Sep. 20152Gb DDR2 - AS4C256M8D2 Features Description - High speed data transfer rates with system frequency up to The AS4C256M8D2 is a eight bank DDR DRAM organized as 400 MHz 8 banks x 32Mbit x 8. The AS4C256M8D2 achieves high - 8 internal banks for concurrent operation speed data transfer rates by employing a chip architecture that - 4-bit prefetch architecture prefetches multiple bits and then synchronizes the output data - Programmable CAS Latency: 3, 4 ,5 , 6 and 7 to a system clock. - Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6 The chip is designed to comply with the following key DDR2 - Write Latency = Read Latency -1 SDRAM features:(1) posted CAS with additive latency, (2) write - Programmable Wrap Sequence: Sequential or Interleave latency = read latency-1, (3) On Die Termination. - Programmable Burst Length: 4 and 8 All of the control, address, circuits are synchronized with the - Automatic and Controlled Precharge Command positive edge of an externally supplied clock. I/O s are synchro- - Power Down Mode nized with a pair of bidirectional strobes (DQS, DQS) in a source - Auto Refresh and Self Refresh synchronous fashion. o o - Refresh Interval: 7.8 us at -40 C Tcase 85 C, Operating the eight memory banks in an interleaved fashion o o 3.9 us at 85 C < Tcase 105 C allows random access operation to occur at a higher rate than is - ODT (On-Die Termination) possible with standard DRAMs. A sequential and gapless data - Weak Strength Data-Output Driver Option rate is possible depending on burst length, CAS latency and - Bidirectional differential Data Strobe (Single-ended data- speed grade of the device. strobe is an optional feature) - On-Chip DLL aligns DQ and DQs transitions with CK transi- tions - DQS can be disabled for single-ended data strobe Table 1: - Read Data Strobe (RDQS) supported (x8 only) - Differential clock inputs CK and CK - JEDEC Power Supply 1.8V 0.1V - VDDQ =1.8V 0.1V - Available in 60-ball FBGA for x8 component - RoHS compliant - tRAS lockout supported Table 1. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP DDR2-800 400 MHz 5 12.5 12.5 Table 2. Ordering Information Product part No Org Temperature Package AS4C256M8D2-25BCN 256M x 8 Commercial (Extended) 60-ball FBGA 0C to +95C AS4C256M8D2-25BIN 256M x 8 Industrial 60-ball FBGA -40C to +95C (Extended) Confidential -2/70- Rev.1.0 Sep. 2015

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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