AS4C32M16D3L-12BCNTR Alliance Memory

AS4C32M16D3L-12BIN AS4C32M16D3L-12BCN Revision History 512M DDR3 AS4C32M16D3L 96ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Sep. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 86 - Rev.1.0 Sep. 2017AS4C32M16D3L-12BIN AS4C32M16D3L-12BCN 32M x 16 bit DDR3L Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Sep. /2017) Features Overview JEDEC Standard Compliant The 512Mb Double-Data-Rate-3L (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.35V (1.283V ~ 1.45V) DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = +1.5V 0.075V DD DDQ DRAM. Operating temperature: The 512Mb chip is organized as 4Mbit x 16 I/Os x 8 - Commercial: T = 0~95 C C bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb - Industrial: T = -40~95 C C /sec/pin for general applications. Supports JEDEC clock jitter specification The chip is designed to comply with all key DDR3L Fully synchronous operation DRAM key features and all of the control and address Fast clock rate: 800MHz inputs are synchronized with a pair of externally supplied Differential Clock, CK & CK differential clocks. Inputs are latched at the cross point Bidirectional differential data strobe of differential clocks (CK rising and CK falling). All I/Os are synchronized with differential DQS pair in a source - DQS & DQS synchronous fashion. 8 internal banks for concurrent operation These devices operate with a single 1.35V -0.067V / 8n-bit prefetch architecture +0.1V power supply and are available in BGA packages. Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 8 x 13 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Org Max Clock (MHz) Product part No Package 800 32M x 16 AS4C32M16D3L-12BCN 96-ball FBGA Commercial 0C to 95C 800 32M x 16 AS4C32M16D3L-12BIN Industrial -40C to 95C 96-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t t (ns) (ns) RCD RP 800 MHz 11 13.75 13.75 DDR3-1600 Confidential - 2 of 86 - Rev.1.0 Sep. 2017