AS4C512M16D3LA Revision History 8Gbit DDR3L SDRAM 8 BANKS X 64Mbit X 16 - Dual Die Package (DDP) 96ball FBGA Package Revision Details Date Rev 1.0 Preliminary datasheet Feb. 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 41 - Rev.1.0 Feb.2019AS4C512M16D3LA Specifications Features - Density : 8G bits - Double-data-rate architecture two data transfers per clock cycle - Organization : - The high-speed data transfer is realized by the 8 bits prefetch pipe- - 64M words x 16 bits x 8 banks lined architecture - Package : - Bi-directional differential data strobe (DQS and DQS ) is transmitted/ - 96-ball FBGA received with data for capturing data at the receiver - Two 512Mbit x 8 dies stacked (DDP) - DQS is edge-aligned with data for READs center-aligned with data - Lead-free (RoHS compliant) and Halogen-free for WRITEs - Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V) - Differential clock inputs (CK and CK) - -Backward compatible to VDD, VDDQ =1.5V 0.075V - DLL aligns DQ and DQS transitions with CK transitions - Data rate : 1866Mbps - Commands entered on each positive CK edge data and data mask - 2KB page size referenced to both edges of DQS - Row address: A0 to A15 - Data mask (DM) for write data - Column address: A0 to A9 - Posted CAS by programmable additive latency for better command - Eight internal banks for concurrent operation and data bus efficiency - Burst lengths (BL) : 8 and 4 with Burst Chop (BC) - On-Die Termination (ODT) for better signal quality - Burst type (BT) : - Synchronous ODT - Sequential (8, 4 with BC) - Dynamic ODT - Interleave (8, 4 with BC) - Asynchronous ODT - CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11, 13 - Multi Purpose Register (MPR) for pre-defined pattern read out - CAS Write Latency (CWL) : 5, 6, 7, 8 ,9 - ZQ calibration for DQ drive and ODT - Precharge : auto precharge option for each burst access - RESET pin for Power-up sequence and reset function - Driver strength : RZQ/7, RZQ/6 (RZQ = 240 ) - SRT range : Normal/extended - Refresh : auto-refresh, self-refresh - Programmable Output driver impedance control - Refresh cycles : - Average refresh period 7.8 s at -40C Tc +85C 3.9 s at +85C < Tc +105C - Operating case temperature range - Comercial Tc = 0C to +95C - Industrial Tc = -40C to +95C - Automotive Tc = -40C to +105C Table 1. Ordering Information Org Temperature Max Clock (MHz) Product part No Package 933 AS4C512M16D3LA-10BCN 512M x 16 96-ball FBGA Commercial 0C to 95C 933 512M x 16 Industrial -40C to 95C 96-ball FBGA AS4C512M16D3LA-10BIN 933 AS4C512M16D3LA-10BAN 96-ball FBGA Automotive -40C to 105C 512M x 16 Table 2. Speed Grade Information CAS Latency tRCD(ns) Speed Grade tRP(ns) Clock Frequency DDR3-1866 933 MHz 13 13.91 13.91 Confidential - 2 of 41 - Rev.1.0 Feb.2019