AS4C512M8D3-12BAN Alliance Memory

4Gb-Auto AS4C512M8D3 Revision History 4Gb Auto-AS4C512M8D3 - 78 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Jun 2015 Rev 2.0 1 Delete Truth Table Note 5 Device state is 4 and 8 burst operation. Apr 2016 . 2 Add follow information in Absolute Maximum DC Ratings note2 Recommended storage temperature is not exceeding 105 C. Do not store at 150 C for more than 1000 hours. Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/83 - Rev.2.0 April 20164Gb-Auto AS4C512M8D3 Features Overview JEDEC Standard Compliant The 4Gb Double-Data-Rate-3 DRAMs is double Power supplies: V & V = +1.5V 0.075V data rate architecture to achieve high-speed DD DDQ operation. It is internally configured as an eight Operating temperature: -40~105 C(TC) bank DRAM. AEC-Q100 Compliant Supports JEDEC clock jitter specification The 4Gb chip is organized as 64Mbit x 8 I/Os x 8 Fully synchronous operation bank devices. These synchronous devices Fast clock rate: 800MHz achieve high speed double-data-rate transfer rates Differential Clock, CK & CK of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 Bidirectional differential data strobe DRAM key features and all of the control and -DQS & DQS address inputs are synchronized with a pair of 8 internal banks for concurrent operation externally supplied differential clocks. Inputs are 8n-bit prefetch architecture latched at the cross point of differential clocks (CK Pipelined internal architecture rising and CK falling). All I/Os are synchronized Precharge & active power down with differential DQS pair in a source synchronous Programmable Mode & Extended Mode registers fashion. Additive Latency (AL): 0, CL-1, CL-2 These devices operate with a single 1.5V 0.075V Programmable Burst lengths: 4, 8 power supply and are available in BGA packages. Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s -40C TC +85C 3.9s +85C TC +105C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 9 x 10.5 x 1.2mm FBGA package - Pb and Halogen Free Table 1. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 800 MHz 11 DDR3-1600 Table 2. Ordering Information Product part No Org Temperature Max Clock (MHz) Package AS4C512M8D3-12BAN Automotive -40C to 105C 800 78-ball FBGA 512Mx 8 Confidential - 2/83 - Rev.2.0 April 2016