AS4C512M8D3LC Revision History 4Gb AS4C512M8D3LC 78 ball FBGA PACKAGE Revision Details Date Rev 1.0 Initial Release June.2020 ALLIANCE MEMORY Inc. reserves the right to change products or specification without notice. 12815 NE 124th Street Suite D, Kirkland, WA 98034 USA Main +1(425)868-4456 Fax:+1 (425)898-8628 Confidential - 1 of 86 - Rev.1.0 June 2020AS4C512M8D3LC 512M x 8 bit DDR3L Synchronous DRAM (SDRAM) Initial Release (Rev. 1.0, June. /20 20) Features Overview JEDEC Standard Compliant The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V =+1.35V (1.283V to 1.45V) DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = +1.5V 0.075V DD DDQ DRAM. Operating temperature: The 4Gb chip is organized as 64Mbit x 8 I/Os x 8 bank - Commercial : T = 0~95 C C devices. These synchronous devices achieve high - Industrial : T = -40~95 C C speed double-data-rate transfer rates of up to 1600 Mb/ sec/pin for general applications. Supports JEDEC clock jitter specification The chip is designed to comply with all key DDR3L Fully synchronous operation DRAM key features and all of the control and address Fast clock rate: 800MHz inputs are synchronized with a pair of externally supplied Differential Clock, CK & CK differential clocks. Inputs are latched at the cross point Bidirectional differential data strobe of differential clocks (CK rising and CK falling). All I/Os - DQS & DQS are synchronized with differential DQS pair in a source 8 internal banks for concurrent operation synchronous fashion. 8n-bit prefetch architecture Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 7.5 x 10.6 x 1.2mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Product part No Max Clock (MHz) Org Package AS4C512M8D3LC-12BCN 512M x 8 Commercial 0C to 95C 800 78-ball FBGA AS4C512M8D3LC-12BIN Industrial -40C to 95C 512M x 8 800 78-ball FBGA Table 2. Speed Grade Information Clock Frequency Speed Grade CAS Latency t (ns) t (ns) RCD RP 11 13.75 800MHZ DDR3 L-1600 13.75 Confidential - 2 of 86 - Rev.1.0 June 2020