AS4C64M16D3B Revision History 1Gb DDR3 AS4C64M 16D3B 96ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Jan. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 86 - Rev.1.0 Jan.2018AS4C64M16D3B 64M x 16 bit DDR3 Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Jan. /201 8) Features Overview JEDEC Standard Compliant The 1Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. Power supplies: V & V = +1.5V 0.075V DD DDQ It is internally configured as an eight bank DRAM. Industrial temperature: The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 : T = 0~95 C - Commercial C bank devices. These synchronous devices achieve - Industrial : T = -40~95 C C high speed double-data-rate transfer rates of up to Supports JEDEC clock jitter specification 1 600 Mb/sec/pin for general applications. Fully synchronous operation The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address Fast clock rate: 800MHz inputs are synchronized with a pair of externally Differential Clock, CK & CK supplied differential clocks. Inputs are latched at the Bidirectional differential data strobe cross point of differential clocks (CK rising and CK - DQS & DQS falling). All I/Os are synchronized with differential DQS 8 internal banks for concurrent operation pair in a source synchronous fashion. 8n-bit prefetch architecture These devices operate with a single 1.5V 0.075V Pipelined internal architecture power supply and are available in BGA packages. Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8 s -40 C TC +85 C 3.9 s +85 C TC +95 C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 9 x 13 x 1.2mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Org Max Clock (MHz) Product part No Package 800 Commercial 0C to 95C 96-ball FBGA AS4C64M16D3B-12BCN 64M x 16 800 Industrial -40C to 95C 96-ball FBGA AS4C64M16D3B-12BIN 64M x 16 Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t t (ns) (ns) RCD RP 800 MHz 11 13.75 13.75 DDR3-1600 Confidential - 2 of 86 - Rev.1.0 Jan.2018