AS4C64M32MD1A-5BIN Revision History 2Gb LPDDR SDRAM AS4C64M32MD1A-5BIN - 90 ball FPBGA PACKAGE Revision Details Date Rev 1.0 Initial Release Nov. 2019 Alliance Memory Inc.12815 NE 124th St, Suite D, Kirkland, WA 98034 USA Tel: +1(425)898-4456 Fax +1(425)896-8628 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 54 - Rev.1.0. Nov. 2019AS4C64M32MD1A-5BIN Features Power Supply VDD/VDDQ = 1.8V/1.8V Double-data-rate architecture two data transfers per clock cycle. Bidirectional data strobe (DQS). Four banks operation. Differential clock inputs (CK and CK ). MRS cycle with address key programs. - CAS Latency (3) - Burst Length (2, 4, 8, 16) - Burst Type (Sequential & Interleave) EMRS cycle with address key programs. - Partial Array Self Refresh (Full, 1/2, 1/4 Array) - Output Driver Strength Control (Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8) Internal Temperature Compensated Self Refresh. All inputs except data & DM are sampled at the positive going edge of the system clock (CK). Data I/O transactions on both edges of data strobe, DM for masking. Edge aligned data output, center aligned data input. No DLL CK to DQS is not synchronized. DM for write masking only. Auto refresh duty cycle. - 7.8us for -40 to 85C Clock stop capability. Package x32 : 8.0 x 13.0mm 90 Ball FPBGA Operating Temperature Range Industrial Type (-40 to +85) Operating Frequency Operating Conditions DDR400 Speed CL2 83MHz(max.) Speed CL3 200MHz(max.) NOTE : 1) CAS Latency Ordering Information Temperature Org Max Clock (MHz) Product part No Package AS4C64M32MD1A-5BIN 200 Hz 64M x 32 Industrial -40C to 85C 9 0-ball FBGA Confidential - 2 of 54 - Rev.1.0. Nov. 2019