128M DDR1 -AS4C8M16D1 Revision History AS4 D - -ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet D 201 O O L D Q F H 0 H P R U , Q F 7 D O R U : D 6 D Q & D U O R V & 7 ( / ) O O L D Q F H 0 H P R U , Q F U H V H U Y H V W K H U L J K W W R F K D Q J H S U R G X F W V R U V S H F L I L F D W L R Q Z L W K R X W Q R W L F H &RQILGHQWLDO 5HY 0D 128M DDR1 -AS4C8M16D1 )HDWXUHV Fast clock rate: 250/200MHz Operating temperature: - Commercial (0C~70 C) - Industrial (-40C~85 C) Differential Clock CK & input CK Bi-directional DQS DLL enable/disable by EMRS Fully synchronous operation Internal pipeline architecture Four internal banks, 2M x 16-bit for each bank Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved Individual byte write mask control DM Write Latency = 0 Auto Refresh and Self Refresh 4096 refresh cycles / 64ms Precharge & active power down Power supplies: VDD & VDDQ = 2.5V 0.2V Interface: SSTL 2 I/O Interface Package: 60-Ball, 8x13x1.2 mm (max) FBGA - Pb free and Halogen free &RQILGHQWLDO 5HY 0D