September 2006 AS7C1025C Advance Information 5V 128K X 8 CMOS SRAM (Center power and ground) Features o o JEDEC-standard package Industrial (-40 to 85 C) temperature. - 32-pin, 400 mil SOJ Organization: 131,072 x 8 bits ESD protection > 2000 volts High speed - 15 ns address access time - 6 ns output enable access time Low power consumption via chip deselect Easy memory expansion with CE, OE inputs Center power and ground Pin arrangement TTL/LVTTL-compatible, three-state I/O Logic block diagram 32-pin SOJ (400 mil) V A16 CC A0 1 32 31 A15 A1 2 GND A2 3 A14 30 A3 4 29 A13 Input buffer CE 5 28 OE I/O0 6 I/O7 27 I/O1 7 26 I/O6 A0 V 8 CC 25 GND A1 I/O7 V GND 9 24 CC A2 I/O5 131,072 x 8 I/O2 10 23 A3 22 I/O3 11 I/O4 Array A4 21 A12 WE 12 A5 (1,048,576) 20 A11 A4 13 A6 19 A10 A5 14 A7 A9 I/O0 A6 15 18 A8 A7 16 17 A8 WE Control Address decoder OE circuit CE 12/5/06, v. 1.0 Alliance Memory P. 1 of 9 Copyright Alliance Memory. All rights reserved. Address decoder A9 A10 A11 A12 A13 A14 A15 A16 Sense amp AS7C1025CAS7C1025C Functional description The AS7C1025C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 15 ns with output enable access times (t ) of 6 ns are ideal for high- AA RC WC OE performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume I power. If the bus is SB static, then full standby power is reached (I ). SB1 A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025C is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.50 +7.0 V CC t1 Voltage on any pin relative to GND V 0.50 V + 0.5 V t2 CC Power dissipation P 1.25 W D o Storage temperature (plastic) T 55 +125 C stg o Ambient temperature with V applied T 55 +125 C CC bias DC current into outputs (low) I 50 mA OUT Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (I , I ) SB SB1 L H H High Z Output disable (I ) CC L H L D Read (I ) OUT CC L L X D Write (I ) IN CC Key: X = dont care, L = low, H = high. 12/5/06, v. 1.0 Alliance Memory P. 2 of 9