Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9272 FEATURES FUNCTIONAL BLOCK DIAGRAM 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) Input-referred noise voltage = 0.75 nV/Hz LOSW-A AD9272 (gain = 21.3 dB) 5 MHz typical LO-A SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB LI-A 12-BIT SERIAL DOUTA+ LNA VGA ADC LG-A LVDS DOUTA Single-ended input V maximum = 733 mV p-p/ IN AAF LOSW-B 550 mV p-p/367 mV p-p LO-B Dual-mode active input impedance matching LI-B 12-BIT DOUTB+ SERIAL LNA VGA ADC LVDS LG-B DOUTB Bandwidth (BW) > 100 MHz AAF LOSW-C Full-scale (FS) output = 4.4 V p-p differential LO-C Variable gain amplifier (VGA) LI-C DOUTC+ 12-BIT SERIAL LNA VGA ADC Attenuator range = 42 dB to 0 dB LG-C LVDS DOUTC AAF LOSW-D SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB LO-D Linear-in-dB gain control LI-D 12-BIT DOUTD+ SERIAL LNA VGA Antialiasing filter (AAF) ADC LG-D LVDS DOUTD AAF LOSW-E Programmable 2nd-order low-pass filter (LPF) from LO-E 8 MHz to 18 MHz LI-E DOUTE+ 12-BIT SERIAL LNA VGA Programmable high-pass filter (HPF) ADC LVDS LG-E DOUTE AAF Analog-to-digital converter (ADC) LOSW-F LO-F 12 bits at 10 MSPS to 80 MSPS LI-F DOUTF+ 12-BIT SERIAL SNR = 70 dB LNA VGA ADC LG-F LVDS DOUTF AAF SFDR = 75 dB LOSW-G Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) LO-G LI-G DOUTG+ 12-BIT Data and frame clock outputs SERIAL LNA VGA LG-G ADC LVDS DOUTG AAF Includes an 8 8 differential crosspoint switch to support LOSW-H continuous wave (CW) Doppler LO-H LI-H Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) 12-BIT DOUTH+ SERIAL LNA VGA ADC LG-H LVDS DOUTH 120 mW per channel in CW Doppler AAF Flexible power-down modes FCO+ Overload recovery in <10 ns FCO Fast recovery from low power standby mode, <2 s REFERENCE DCO+ SWITCH 100-lead TQFP DCO ARRAY APPLICATIONS Medical imaging/ultrasound Automotive radar GENERAL DESCRIPTION Figure 1. The AD9272 is designed for low cost, low power, small size, and The LNA has a single-ended-to-differential gain that is selectable ease of use. It contains eight channels of a low noise preamplifier through the SPI. The LNA input-referred noise voltage is typically (LNA) with a variable gain amplifier (VGA), an antialiasing 0.75 nV/Hz at a gain of 21.3 dB, and the combined input-referred filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-to- noise voltage of the entire channel is 0.85 nV/Hz at maximum digital converter (ADC). gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB Each channel features a variable gain range of 42 dB, a fully LNA gain, the input SNR is about 92 dB. In CW Doppler mode, differential signal path, an active input preamplifier termination, a the LNA output drives a transconductance amp that is switched maximum gain of up to 52 dB, and an ADC with a conversion through an 8 8 differential crosspoint switch. The switch is rate of up to 80 MSPS. The channel is optimized for dynamic programmable through the SPI. performance and low power in applications where a small package size is critical. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CWD 7:0 + AND CWD 7:0 GAIN+ AVDD1 GAIN AVDD2 PDWN VREF STBY RBIAS CSB SERIAL SCLK PORT INTERFACE SDIO DRVDD DATA CLK+ RATE CLK MULTIPLIER 07029-001AD9272 TABLE OF CONTENTS Features .............................................................................................. 1 Ultrasound .................................................................................. 21 Applications ....................................................................................... 1 Channel Overview ..................................................................... 22 General Description ......................................................................... 1 Input Overdrive .......................................................................... 25 Functional Block Diagram .............................................................. 1 CW Doppler Operation ............................................................. 25 Revision History ............................................................................... 2 TGC Operation ........................................................................... 27 Product Highlights ........................................................................... 3 ADC ............................................................................................. 31 Specif icat ions ..................................................................................... 4 Clock Input Considerations ...................................................... 31 AC Specifications .......................................................................... 4 Serial Port Interface (SPI) .............................................................. 38 Digital Specifications ................................................................... 8 Hardware Interface ..................................................................... 38 Switching Specifications .............................................................. 9 Memory Map .................................................................................. 40 Absolute Maximum Ratings .......................................................... 11 Reading the Memory Map Table .............................................. 40 Thermal Impedance ................................................................... 11 Reserved Locations .................................................................... 40 ESD Caution ................................................................................ 11 Default Values ............................................................................. 40 Pin Configuration and Function Descriptions ........................... 12 Logic Levels ................................................................................. 40 Typical Performance Characteristics ........................................... 15 Outline Dimensions ....................................................................... 44 Equivalent Circuits ......................................................................... 19 Ordering Guide .......................................................................... 44 Theory of Operation ...................................................................... 21 REVISION HISTORY 7/09Rev. B to Rev. C Changes to Input Overload Protection Section and Figure 43 ....... 25 Changes to Digital Outputs and Timing Section and Changes to Figure 63 ...................................................................................... 33 Changes to Hardware Interface Section ...................................... 39 6/09Rev. A to Rev. B Changes to Product Highlights Section ......................................... 3 Changes to Table 1 ............................................................................ 4 Changes to Absolute Maximum Ratings Table ........................... 11 Changes to Figure 22 ...................................................................... 17 Changes to Figure 33 and Figure 34 ............................................. 20 Changes to Low Noise Amplifier (LNA) Section ....................... 22 Changes to Active Impedance Matching Section ....................... 23 Changes to Figure 39 ...................................................................... 23 Changes to LNA Noise Section ..................................................... 24 Changes to Figure 47 ...................................................................... 28 Changes to Figure 48 and Figure 49 ............................................. 29 Changes to CSB Pin Section .......................................................... 36 Changes to Reading the Memory Map Table Section................ 40 4/09Revision A: Initial Version Rev. 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