1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs AD9511 FEATURES FUNCTIONAL BLOCK DIAGRAM VS GND RSET CPRSET VCP Low phase noise phase-locked loop core Reference input frequencies to 250 MHz PLL DISTRIBUTION AD9511 REF REF Programmable dual-modulus prescaler REFIN R DIVIDER Programmable charge pump (CP) current PHASE CHARGE REFINB FREQUENCY CP PUMP DETECTOR Separate CP supply (VCP ) extends tuning range S N DIVIDER SYNCB, Two 1.6 GHz, differential clock inputs FUNCTION RESETB PLL PDB STATUS SETTINGS 5 programmable dividers, 1 to 32, all integers CLK1 CLK2 Phase select for output-to-output coarse delay adjust CLK2B CLK1B PROGRAMMABLE 3 independent 1.2 GHz LVPECL outputs DIVIDERS AND LVPECL PHASE ADJUST Additive output jitter 225 fs rms OUT0 /1, /2, /3... /31, /32 OUT0B 2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs LVPECL Additive output jitter 275 fs rms OUT1 /1, /2, /3... /31, /32 OUT1B Fine delay adjust on 1 LVDS/CMOS output LVPECL Serial control port OUT2 /1, /2, /3... /31, /32 OUT2B Space-saving 48-lead LFCSP SCLK LVDS/CMOS SERIAL OUT3 SDIO CONTROL /1, /2, /3... /31, /32 SDO PORT OUT3B APPLICATIONS CSB LVDS/CMOS OUT4 /1, /2, /3... /31, /32 T Low jitter, low phase noise clock distribution OUT4B DELAY Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs ADJUST High performance wireless transceivers Figure 1. High performance instrumentation Broadband infrastructure Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock GENERAL DESCRIPTION output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing The AD9511 provides a multi-output clock distribution adjustment. One of the LVDS/CMOS outputs features a function along with an on-chip PLL core. The design programmable delay element with full-scale ranges up to 10 ns emphasizes low jitter and phase noise to maximize data of delay. This fine tuning delay block has 5-bit resolution, converter performance. Other applications with demanding giving 32 possible delays from which to choose for each full- phase noise and jitter requirements also benefit from this part. scale setting. The PLL section consists of a programmable reference divider The AD9511 is ideally suited for data converter clocking (R) a low noise phase frequency detector (PFD) a precision applications where maximum converter performance is charge pump (CP) and a programmable feedback divider (N). achieved by encode signals with subpicosecond jitter. By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6 GHz may be synchronized to the The AD9511 is available in a 48-lead LFCSP and can be input reference. operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by There are five independent clock outputs. Three outputs are connecting the charge pump supply (VCP) to 5.5 V. The LVPECL (1.2 GHz), and two are selectable as either LVDS temperature range is 40C to +85C. (800 MHz) or CMOS (250 MHz) levels. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. 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All rights reserved. 05286-001AD9511 TABLE OF CONTENTS Specifications .................................................................................... 4 A and B Counters ................................................................... 30 PLL Characteristics ...................................................................... 4 Determining Values for P, A, B, and R ............................... 30 Clock Inputs .................................................................................. 5 Phase Frequency Detector (PFD) and Charge Pump ....... 31 Clock Outputs ............................................................................... 6 Antibacklash Pulse ................................................................. 31 Timing Characteristics ................................................................ 7 STATUS Pin ........................................................................... 31 Clock Output Phase Noise .......................................................... 9 PLL Digital Lock Detect ........................................................ 31 Clock Output Additive Time Jitter .......................................... 12 PLL Analog Lock Detect ....................................................... 32 PLL and Distribution Phase Noise and Spurious .................. 14 Loss of Reference .................................................................... 32 Serial Control Port ..................................................................... 15 FUNCTION Pin ......................................................................... 32 FUNCTION Pin ......................................................................... 15 RESETB: 58h<6:5> = 00b (Default) .................................... 32 STATUS Pin ................................................................................ 16 SYNCB: 58h<6:5> = 01b ....................................................... 32 Power ........................................................................................... 16 PDB: 58h<6:5> = 11b ............................................................ 33 Timing Diagrams ............................................................................ 17 Distribution Section ................................................................... 33 Absolute Maximum Ratings ......................................................... 18 CLK1 and CLK2 Clock Inputs ................................................. 33 Thermal Characteristics ............................................................ 18 Dividers ....................................................................................... 33 ESD Caution................................................................................ 18 Setting the Divide Ratio ........................................................ 33 Pin Configuration and Function Descriptions .......................... 19 Setting the Duty Cycle ........................................................... 33 Terminology .................................................................................... 21 Divider Phase Offset .............................................................. 37 Typical Performance Characteristics ........................................... 22 Delay Block ................................................................................. 38 Typical Modes of Operation ......................................................... 26 Calculating the Delay ............................................................ 38 PLL with External VCXO/VCO Followed by Clock Outputs ........................................................................................ 38 Distribution ................................................................................. 26 Power-Down Modes .................................................................. 39 Clock Distribution Only ............................................................ 26 Chip Power-Down or Sleep ModePDB .......................... 39 PLL with External VCO and Band-Pass Filter Followed by PLL Power-Down .................................................................. 39 Clock Distribution ..................................................................... 27 Distribution Power-Down .................................................... 39 Functional Description .................................................................. 29 Individual Clock Output Power-Down .............................. 39 Overall .......................................................................................... 29 Individual Circuit Block Power-Down ............................... 39 PLL Section ................................................................................. 29 Reset Modes ................................................................................ 40 PLL Reference InputREFIN .............................................. 29 Power-On ResetStart-Up Conditions when VS is VCO/VCXO Clock InputCLK2 ....................................... 29 Applied .................................................................................... 40 PLL Reference DividerR .................................................... 29 Asynchronous Reset via the FUNCTION Pin ................... 40 VCO/VCXO Feedback DividerN (P, A, B) .................... 29 Soft Reset via the Serial Port ................................................. 40 Rev. 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