12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO Data Sheet AD9520-1 FEATURES FUNCTIONAL BLOCK DIAGRAM CP LF Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.27 GHz to 2.65 GHz OPTIONAL STATUS Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz REF1 MONITOR REFIN 1 differential or 2 single-ended reference inputs VCO Accepts CMOS, LVDS, or LVPECL references to 250 MHz REFIN REF2 Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler ZERO DELAY Reference monitoring capability DIVIDER CLK AND MUXES Automatic/manual reference holdover and reference LVPECL/ CMOS switchover modes, with revertive switching OUT0 OUT1 DIV/ Glitch-free switchover between references OUT2 Automatic recovery from holdover OUT3 OUT4 DIV/ Digital or analog lock detect, selectable OUT5 Optional zero delay operation OUT6 DIV/ OUT7 Twelve 1.6 GHz LVPECL outputs divided into 4 groups OUT8 Each group of 3 outputs shares a 1-to-32 divider with OUT9 DIV/ OUT10 phase delay OUT11 Additive output jitter as low as 225 fs rms 2 SPI/I C CONTROL Channel-to-channel skew grouped outputs < 16 ps PORT AND EEPROM AD9520 DIGITAL LOGIC Each LVPECL output can be configured as 2 CMOS outputs (for f 250 MHz) OUT Figure 1. Automatic synchronization of all outputs on power-up Manual output synchronization available SPI- and IC-compatible serial control port 64-lead LFCSP The AD9520-1 serial interface supports both SPI and IC ports. Nonvolatile EEPROM stores configuration settings An in-package EEPROM, which can be programmed through the serial interface, can store user-defined register settings for APPLICATIONS power-up and chip reset. Low jitter, low phase noise clock distribution The AD9520-1 features 12 LVPECL outputs in four groups. Any Clock generation and translation for SONET, 10Ge, 10GFC, of the 1.6 GHz LVPECL outputs can be reconfigured as two Synchronous Ethernet, OTU2/3/4 250 MHz CMOS outputs. If an application requires LVDS Forward error correction (G.710) drivers instead of LVPECL drivers, refer to the AD9522-1. Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers Each group of three outputs has a divider that allows both the ATE and high performance instrumentation divide ratio (from 1 to 32) and the phase offset or coarse time Broadband infrastructures delay to be set. The AD9520-1 is available in a 64-lead LFCSP and can be operated GENERAL DESCRIPTION from a single 3.3 V supply. The external VCO can have an 1 The AD9520-1 provides a multioutput clock distribution operating voltage of up to 5.5 V. A separate output driver power function with subpicosecond jitter performance, along with an supply can be from 2.375 V to 3.465 V. on-chip PLL and VCO. The on-chip VCO tunes from 2.27 GHz The AD9520-1 is specified for operation over the standard to 2.65 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz industrial range of 40C to +85C. can also be used. 1 AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-1 is used, it refers to that specific member of the AD9520 family. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com SWITCHOVER AND MONITOR PLL 07214-001AD9520-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions ........................... 18 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 21 General Description ......................................................................... 1 Terminology .................................................................................... 26 Functional Block Diagram .............................................................. 1 Detailed Block Diagram ................................................................ 27 Revision History ............................................................................... 3 Theory of Operation ...................................................................... 28 Specifications ..................................................................................... 4 Operational Configurations ...................................................... 28 Power Supply Requirements ....................................................... 4 Zero Delay Operation ................................................................ 42 PLL Characteristics ...................................................................... 4 Clock Distribution ..................................................................... 43 Clock Inputs .................................................................................. 7 Reset Modes ................................................................................ 49 Clock Outputs ............................................................................... 7 Power-Down Modes .................................................................. 50 Timing Characteristics ................................................................ 8 Serial Control Port ......................................................................... 51 Clock Output Additive Phase Noise (Distribution Only VCO SPI/IC Port Selection ................................................................ 51 Divider Not Used) ...................................................................... 10 IC Serial Port Operation .......................................................... 51 Clock Output Absolute Phase Noise (Internal VCO Used) .. 11 SPI Serial Port Operation .......................................................... 54 Clock Output Absolute Time Jitter (Clock Generation Using SPI Instruction Word (16 Bits) ................................................. 55 Internal VCO) ............................................................................. 11 SPI MSB/LSB First Transfers .................................................... 55 Clock Output Absolute Time Jitter (Clock Cleanup Using EEPROM Operations ..................................................................... 58 Internal VCO) ............................................................................. 11 Writing to the EEPROM ........................................................... 58 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ......................................................................... 12 Reading from the EEPROM ..................................................... 58 Clock Output Additive Time Jitter (VCO Divider Not Used) Programming the EEPROM Buffer Segment ......................... 59 ....................................................................................................... 12 Thermal Performance .................................................................... 60 Clock Output Additive Time Jitter (VCO Divider Used) ..... 12 Register Map ................................................................................... 61 Serial Control PortSPI Mode ................................................ 13 Register Map Descriptions ............................................................ 64 Serial Control PortIC Mode ................................................ 14 Applications Information .............................................................. 77 PD, EEPROM, RESET, and SYNC Pins .................................. 15 Frequency Planning Using the AD9520 .................................. 77 Serial Port Setup PinsSP1, SP0 ............................................. 15 Using the AD9520 Outputs for ADC Clock Applications .... 77 LD, STATUS, and REFMON Pins ............................................ 15 LVPECL Clock Distribution ..................................................... 78 Power Dissipation ....................................................................... 16 CMOS Clock Distribution ........................................................ 78 Absolute Maximum Ratings .......................................................... 17 Outline Dimensions ....................................................................... 80 Thermal Resistance .................................................................... 17 Ordering Guide .......................................................................... 80 ESD Caution ................................................................................ 17 Rev. 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