Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs Data Sheet AD9523-1 FEATURES FUNCTIONAL BLOCK DIAGRAM Output frequency: <1 MHz to 1 GHz OSC IN, OSC IN Start-up frequency accuracy: <100 ppm (determined by OUT0, AD9523-1 OUT0 VCXO reference accuracy) REFA, OUT3, Zero delay operation REFA OUT3 DIVIDE-BY- REFB, 8 OUTPUTS Input-to-output edge timing: <150 ps PLL1 PLL2 3, 4, 5 OUT10, REFB OUT10 Dual VCO dividers REF TEST 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS OUT13, OUT13 14 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 resolution steps of period of VCO OUT4, SCLK/SCL CONTROL OUT4 output divider SDIO/SDA INTERFACE DIVIDE-BY- 2 (SPI AND I C) 6 OUTPUTS SDO 3, 4, 5 Output-to-output skew: <50 ps OUT9, OUT9 ZERO Duty cycle correction for odd divider settings DELAY Automatic synchronization of all outputs on power-up 14-CLOCK EEPROM DISTRIBUTION Absolute output jitter: <150 fs at 122.88 MHz Integration range: 12 kHz to 20 MHz ZD IN, ZD IN Broadband timing jitter: 124 fs Figure 1. Digital lock detect Nonvolatile EEPROM stores configuration settings GENERAL DESCRIPTION SPI- and IC-compatible serial control port The AD9523-1 provides a low power, multi-output, clock Dual PLL architecture distribution function with low jitter performance, along with an PLL1 on-chip PLL and VCO with two VCO dividers. The on-chip VCO Low bandwidth for reference input clock cleanup with tunes from 2.94 GHz to 3.1 GHz. external VCXO The AD9523-1 is designed to support the clock requirements Phase detector rate up to 130 MHz for long term evolution (LTE) and multicarrier GSM base Redundant reference inputs station designs. It relies on an external VCXO to provide the Automatic and manual reference switchover modes reference jitter cleanup to achieve the restrictive low phase noise Revertive and nonrevertive switching requirements necessary for acceptable data converter SNR Loss of reference detection with holdover mode performance. Low noise LVCMOS output from VCXO used for RF/IF synthesizers The input receivers, oscillator, and zero delay receiver provide PLL2 both single-ended and differential operation. When connected Phase detector rate up to 259 MHz to a recovered system reference clock and a VCXO, the device Integrated low noise VCO generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). APPLICATIONS The frequency and phase of one clock output relative to another LTE and multicarrier GSM base stations clock output can be varied by means of a divider phase select Wireless and broadband infrastructure function that serves as a jitter-free, coarse timing adjustment Medical instrumentation in increments that are equal to half the period of the signal Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs coming out of the VCO. Low jitter, low phase noise clock distribution An in-package EEPROM can be programmed through the serial Clock generation and translation for SONET, 10Ge, 10G FC, interface to store user-defined register settings for power-up and other 10 Gbps protocols and chip reset. Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 09278-001AD9523-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 22 Applications ....................................................................................... 1 Detailed Block Diagram ............................................................ 22 Functional Block Diagram .............................................................. 1 Overview ..................................................................................... 22 General Description ......................................................................... 1 Component BlocksInput PLL (PLL1) .................................. 23 Revision History ............................................................................... 3 Component BlocksOutput PLL (PLL2) .............................. 24 Specifications ..................................................................................... 4 Clock Distribution ..................................................................... 26 Conditions ..................................................................................... 4 Zero Delay Operation ................................................................ 28 Supply Current .............................................................................. 4 Lock Detect ................................................................................. 28 Power Dissipation ......................................................................... 6 Reset Modes ................................................................................ 28 REFA, REFA, REFB, REFB, OSC IN, OSC IN, and ZD IN, Power-Down Mode .................................................................... 29 ZD IN Input Characteristics ...................................................... 7 Power Supply Sequencing ......................................................... 29 OSC CTRL Output Characteristics .......................................... 7 Serial Control Port ......................................................................... 30 REF TEST Input Characteristics ............................................... 7 SPI/IC Port Selection ................................................................ 30 PLL1 Output Characteristics ...................................................... 8 IC Serial Port Operation .......................................................... 30 OUT0, OUT0 to OUT13, OUT13 Distribution Output SPI Serial Port Operation .......................................................... 33 Characteristics .............................................................................. 8 SPI Instruction Word (16 Bits) ................................................. 34 Timing Alignment Characteristics ............................................ 9 SPI MSB/LSB First Transfers .................................................... 34 Jitter and Noise Characteristics ................................................ 10 EEPROM Operations ..................................................................... 37 PLL2 Characteristics .................................................................. 10 Writing to the EEPROM ........................................................... 37 PD SYNC RESET Logic Input Pins , , , EEPROM SEL, Reading from the EEPROM ..................................................... 37 REF SEL ...................................................................................... 10 Programming the EEPROM Buffer Segment ......................... 38 Status Output PinsSTATUS1, STATUS0 ............................. 11 Device Initialization Flowcharts ................................................... 40 Serial Control PortSPI Mode ................................................ 11 Power Dissipation and Thermal Considerations ....................... 43 Serial Control PortIC Mode ................................................ 12 Clock Speed and Driver Mode ................................................. 43 Absolute Maximum Ratings .......................................................... 13 Evaluation of Operating Conditions ........................................ 43 Thermal Resistance .................................................................... 13 Thermally Enhanced Package Mounting Guidelines ............ 44 ESD Caution ................................................................................ 13 Control Registers ............................................................................ 45 Pin Configuration and Function Descriptions ........................... 14 Control Register Map ................................................................ 45 Typical Performance Characteristics ........................................... 17 Control Register Map Bit Descriptions ................................... 50 Input/Output Termination Recommendations .......................... 20 Outline Dimensions ....................................................................... 63 Terminology .................................................................................... 21 Ordering Guide .......................................................................... 63 Rev. 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