AD9530BCPZ

4 CML Output, Low Jitter Clock Generator with an Integrated 5.4 GHz VCO Data Sheet AD9530 FEATURES GENERAL DESCRIPTION Fully integrated, ultralow noise phase-locked loop (PLL) The AD9530 is a fully integrated PLL and distribution supporting, 4 differential, 2.7 GHz common-mode logic (CML) outputs clock cleanup, and frequency translation device for 40 Gbps/ 2 differential reference inputs with programmable internal 100 Gbps OTN applications. The internal PLL can lock to one termination options of two reference frequencies to generate four discrete output <232 fs rms absolute jitter (12 kHz to 20 MHz) with a non- frequencies up to 2.7 GHz. ideal reference and 8 kHz loop bandwidth The AD9530 features an internal 5.11 GHz to 5.4 GHz, ultralow <100 fs rms absolute jitter (12 kHz to 20 MHz) with an 80 kHz noise voltage controlled oscillator (VCO). All four outputs are loop bandwidth and low jitter input reference clock individually divided down from the internal VCO using two high Supports low loop bandwidths for jitter attenuation speed VCO dividers (the Mx dividers) and four individual 8-bit Manual switchover channel dividers (the Dx dividers). The high speed VCO dividers Single 2.5 V typical supply voltage offer fixed divisions of 2, 2.5, 3, and 3.5 for wide coverage of 48-lead, 7 mm 7 mm LFCSP possible output frequencies. The AD9530 is configurable for APPLICATIONS loop bandwidths <15 kHz to attenuate reference noise. 40 Gbps/100 Gbps optical transport network (OTN) line side The AD9530 is available in a 48-lead LFCSP and operates from a clocking single 2.5 V typical supply voltage. Clocking of high speed analog-to-digital converters (ADCs) The AD9530 operates over the extended industrial temperature and digital-to-analog converters (DACs) range of 40C to +85C. Data communications FUNCTIONAL BLOCK DIAGRAM REF SEL OUT1 AD9530 D1 DIVIDER (1 TO 255) OUT1 REFA OUT2 D2 DIVIDER M1 DIVIDER REFA (1 TO 255) 2, 2.5, 3, 3.5 OUT2 R DIVIDER 800MHz MAX PLL (1 TO 255) OUT3 REFB D3 DIVIDER M2 DIVIDER (1 TO 255) 2, 2.5, 3, 3.5 OUT3 REFB OUT4 D4 DIVIDER SERIAL PORT AND (1 TO 255) OUT4 CONTROL LOGIC SDIO SDO SCLK CS LD CML 50 SOURCE TERMINATED 2.7GHz MAX Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 14044-001AD9530 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 27 Applications ....................................................................................... 1 Power Supply Recommendations ............................................. 27 General Description ......................................................................... 1 Using the AD9530 Outputs for ADC Clock Applications .... 27 Functional Block Diagram .............................................................. 1 Typical Application Block Diagram ......................................... 28 Revision History ............................................................................... 3 Control Registers ............................................................................ 29 Specifications ..................................................................................... 4 Control Register Map Overview .............................................. 29 Supply Voltage and Temperature Range .................................... 4 Control Register Map Descriptions ............................................. 31 Supply Current .............................................................................. 4 SPI Configuration (Register 0x000 to Register 0x001) ......... 31 Power Dissipation ......................................................................... 5 Status (Register 0x002) .............................................................. 32 REFA and REFB Input Characteristics ...................................... 6 Chip Type (Register 0x003) ...................................................... 32 PLL Characteristics ...................................................................... 7 Product ID (Register 0x004 to Register 0x005)...................... 32 PLL Digital Lock Detect .............................................................. 7 Part Version (Register 0x006) ................................................... 33 Clock Outputs (Internal Termination Disabled) ..................... 7 User Scratchpad 1 (Register 0x00A) ........................................ 33 Clock Outputs (Internal Termination Enabled) ....................... 8 SPI Version (Register 0x00B) .................................................... 33 Clock Output Absolute Time Jitter (Low Loop Vendor ID (Register 0x00C to Register 0x00D) ..................... 33 Bandwidth) .................................................................................... 9 IO UPDATE (Register 0x00F) ................................................. 33 Clock Output Absolute Time Jitter (High Loop R Divider (Reference Input Divider) (Register 0x010) ......... 33 Bandwidth) .................................................................................. 10 R Divider Control (Register 0x011) ......................................... 34 RESET and REF SEL Pins ........................................................ 10 Reference Input A (Register 0x012) ......................................... 34 LD Pin .......................................................................................... 10 Reference Input B (Register 0x013) ......................................... 34 Serial Control Port ..................................................................... 10 OUT1 Divider (Register 0x014) ............................................... 35 Absolute Maximum Ratings .......................................................... 12 OUT1 Driver Control Register (Register 0x015) ................... 35 Thermal Resistance .................................................................... 12 OUT2 Divider (Register 0x016) ............................................... 35 ESD Caution ................................................................................ 12 OUT2 Driver Control (Register 0x017) .................................. 35 Pin Configuration and Function Descriptions ........................... 13 OUT3 Divider (Register 0x018) ............................................... 36 Typical Performance Characteristics ........................................... 15 OUT3 Driver Control (Register 0x019) .................................. 36 Terminology .................................................................................... 17 OUT4 Divider (Register 0x01A) .............................................. 36 Theory of Operation ...................................................................... 18 OUT4 Driver Control (Register 0x01B) .................................. 36 Detailed Functional Block Diagram ........................................ 18 VCO Power (Register 0x01C) ................................................... 37 Overview ...................................................................................... 18 PLL Lock Detect Control (Register 0x01D) ........................... 37 Configuration of the PLL .......................................................... 18 PLL Lock Detect Readback (Registers 0x01E to 0x01F) ....... 37 Reset Modes ................................................................................ 21 M1, M2, M3 Dividers (Register 0x020 to Register 0x022) ... 38 Power-Down Modes................................................................... 21 M3 Divider (Register 0x022) .................................................... 39 Input/Output Termination Recommendations .......................... 22 N Divider (Register 0x023) ....................................................... 39 Serial Control Port .......................................................................... 23 N Divider Control (Register 0x024) ........................................ 39 SPI Serial Port Operation .......................................................... 23 Charge Pump (Register 0x025) ................................................ 39 Power Dissipation and Thermal Considerations ....................... 26 Phase Frequency Dectector (Register 0x026) ......................... 39 Clock Speed and Driver Mode ................................................. 26 Loop Filter (Register 0x027) ..................................................... 40 Evaluation of Operating Conditions ........................................ 26 VCO Frequency (Register 0x028) ............................................ 40 Thermally Enhanced Package Mounting Guidelines ............ 26 User Scratchpad2 (Register 0x0FE) ......................................... 40 Rev. 0 Page 2 of 41