Product Information

AD9549ABCPZ

AD9549ABCPZ electronic component of Analog Devices

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Clock Generators & Support Products Dual Input Network Sync

Manufacturer: Analog Devices
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27: USD 38.0529 ea
Line Total: USD 1027.43

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MOQ: 27  Multiples: 1
Pack Size: 1
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AD9549ABCPZ
Analog Devices

1 : USD 44.746
10 : USD 41.717
25 : USD 38.975
100 : USD 35.225
250 : USD 34.15
500 : USD 33.325

     
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Dual Input Network Clock Generator/Synchronizer AD9549 FEATURES APPLICATIONS Flexible reference inputs Network synchronization Input frequencies: 8 kHz to 750 MHz Reference clock jitter cleanup Two reference inputs SONET/SDH clocks up to OC-192, including FEC Loss of reference indicators Stratum 3/3E reference clocks Auto and manual holdover modes Wireless base station, controllers Auto and manual switchover modes Cable infrastructure Smooth A-to-B phase transition on outputs Data communications Excellent stability in holdover mode GENERAL DESCRIPTION Programmable 16 + 1-bit input divider, R The AD9549 provides synchronization for many systems, Differential HSTL clock output including synchronous optical networks (SONET/SDH). The Output frequencies to 750 MHz AD9549 generates an output clock, synchronized to one of two Low jitter clock doubler for frequencies of >400 MHz external input references. The external references may contain Single-ended CMOS output for frequencies of <150 MHz significant time jitter, also specified as phase noise. Using a Programmable digital loop filter (<1 Hz to ~100 kHz) digitally controlled loop and holdover circuitry, the AD9549 High speed digitally controlled oscillator (DCO) core continues to generate a clean (low jitter), valid output clock during Direct digital synthesizer (DDS) with integrated 14-bit DAC a loss of reference condition, even when both references have failed. Excellent dynamic performance Programmable 16 + 1-bit feedback divider, S The AD9549 operates over an industrial temperature range of Software controlled power-down 40C to +85C. Available 64-lead LFCSP package BASIC BLOCK DIAGRAM AD9549 S1 TO S4 FDBK IN FILTER DAC OUT REFERENCE REFA IN OUT DIGITAL PLL CLOCK R MONITORS R, S DIVIDERS OUTPUT AND HOLDOVER DRIVERS OUT CMOS REFB IN SWITCHING SERIAL PORT, SYSTEM CLOCK I/O LOGIC MULTIPLIER DIGITAL INTERFACE Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 20072010 Analog Devices, Inc. All rights reserved. 06744-001AD9549 TABLE OF CONTENTS Features .............................................................................................. 1 Power-Up ......................................................................................... 42 Applications ....................................................................................... 1 Power-On Reset .......................................................................... 42 General Description ......................................................................... 1 Programming Sequence ............................................................ 42 Basic Block Diagram ........................................................................ 1 Power Supply Partitioning ............................................................. 43 Revision History ............................................................................... 3 3.3 V Supplies .............................................................................. 43 Specifications ..................................................................................... 4 1.8 V Supplies .............................................................................. 43 DC Specifications ......................................................................... 4 Serial Control Port ......................................................................... 44 AC Specifications .......................................................................... 6 Serial Control Port Pin Descriptions ....................................... 44 Absolute Maximum Ratings ............................................................ 9 Operation of Serial Control Port .............................................. 44 Thermal Resistance ...................................................................... 9 The Instruction Word (16 Bits) ................................................ 45 ESD Caution .................................................................................. 9 MSB/LSB First Transfers ........................................................... 45 Pin Configuration and Function Descriptions ........................... 10 I/O Register Map ............................................................................ 48 Typical Performance Characteristics ........................................... 13 I/O Register Descriptions .............................................................. 53 Input/Output Termination Recommendations .......................... 16 Serial Port Configuration (Register 0x0000 to Register 0x0005) ........................................................................................ 53 Theory of Operation ...................................................................... 17 Power-Down and Reset (Register 0x0010 to Register 0x0013) Overview ...................................................................................... 17 ....................................................................................................... 53 Digital PLL Core (DPLLC)........................................................ 17 System Clock (Register 0x0020 to Register 0x0023) ............. 54 Phase Detector ............................................................................ 21 Digital PLL Control and Dividers (Register 0x0100 to Digital Loop Filter Coefficients ................................................ 22 Register 0x0130) ......................................................................... 55 Closed-Loop Phase Offset ......................................................... 24 Free-Run (Single-Tone) Mode (Register 0x01A0 to Register Lock Detection ............................................................................ 24 0x01AD) ...................................................................................... 61 Reference Monitors .................................................................... 26 Reference Selector/Holdover (Register 0x01C0 to Register 0x01C3) ........................................................................................ 62 Reference Switchover ................................................................. 27 Doubler and Output Drivers (Register 0x0200 to Register Holdover ...................................................................................... 29 0x0201) ........................................................................................ 63 Output Frequency Range Control ............................................ 32 Monitor (Register 0x0300 to Register 0x0335)....................... 64 Reconstruction Filter ................................................................. 32 Calibration (User-Accessible Trim) (Register 0x0400 to FDBK IN Inputs ........................................................................ 33 Register 0x0410) ......................................................................... 70 Reference Inputs ......................................................................... 33 Harmonic Spur Reduction (Register 0x0500 to Register SYSCLK Inputs ........................................................................... 33 0x0509) ........................................................................................ 71 Harmonic Spur Reduction ........................................................ 35 Applications Information .............................................................. 73 Output Clock Drivers and 2 Frequency Multiplier ............. 36 Sample Applications Circuit ..................................................... 73 Frequency Slew Limiter ............................................................. 37 Outline Dimensions ....................................................................... 74 Frequency Estimator .................................................................. 37 Ordering Guide .......................................................................... 74 Status and Warnings ................................................................... 39 Thermal Performance .................................................................... 41 Rev. D Page 2 of 76

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8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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