Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter Data Sheet AD9653 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD 1.8 V supply operation Low power: 164 mW per channel at 125 MSPS SERIAL D0+A 16 VIN+A LVDS PIPELINE DIGITAL D0A SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span) VINA ADC SERIALIZER D1+A SERIAL SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span) LVDS D1A 16 VIN+B SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span) PIPELINE DIGITAL D0+B SERIAL VINB ADC SERIALIZER LVDS D0B DNL = 0.7 LSB INL = 3.5 LSB (2.0 V p-p input span) RBIAS SERIAL D1+B VREF Serial LVDS (ANSI-644, default) and low power, reduced LVDS D1B SENSE FCO+ range option (similar to IEEE 1596.3) 1V AD9653 REF FCO SELECT 650 MHz full power analog bandwidth D0+C SERIAL AGND LVDS D0C 2 V p-p input voltage range (supports up to 2.6 V p-p) 16 VIN+C DIGITAL PIPELINE D1+C SERIAL Serial port control SERIALIZER ADC VINC LVDS D1C Full chip and individual channel power-down modes D0+D SERIAL 16 VIN+D LVDS D0D PIPELINE DIGITAL Flexible bit orientation ADC SERIALIZER VIND D1+D SERIAL Built-in and custom digital test pattern generation LVDS D1D SERIAL PORT DCO+ CLOCK Multichip sync and clock divider INTERFACE VCM MANAGEMENT DCO Programmable output clock and data alignment Standby mode APPLICATIONS Medical ultrasound and MRI Figure 1. High speed imaging Quadrature radio receivers Diversity radio receivers as programmable output clock and data alignment and digital Test equipment test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with GENERAL DESCRIPTION custom user-defined test patterns entered via the serial port The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital interface (SPI). converter (ADC) with an on-chip sample-and-hold circuit The AD9653 is available in a RoHS-compliant, 48-lead LFCSP. designed for low cost, low power, small size, and ease of use. It is specified over the industrial temperature range of 40C to The product operates at a conversion rate of up to 125 MSPS +85C. and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. PRODUCT HIGHLIGHTS The ADC requires a single 1.8 V power supply and LVPECL-/ 1. Small Footprint. CMOS-/LVDS-compatible sample rate clock for full performance Four ADCs are contained in a small, space-saving package. operation. No external reference or driver components are 2. Low power of 164 mW/channel at 125 MSPS with scalable required for many applications. power options. 3. Pin compatible to the AD9253 14-bit quad and the AD9633 The ADC automatically multiplies the sample rate clock for the 12-bit quad ADC. appropriate LVDS serial data rate. A data clock output (DCO) for 4. Ease of Use. capturing data on the output and a frame clock output (FCO) A data clock output (DCO) operates at frequencies of up to for signaling a new output byte are provided. Individual channel 500 MHz and supports double data rate (DDR) operation. power-down is supported and typically consumes less than 2 mW 5. User Flexibility. when all channels are disabled. The ADC contains several features The SPI control offers a wide range of flexible features to designed to maximize flexibility and minimize system cost, such meet specific system requirements. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com CSB SDIO/OLM SCLK/DTP SYNC CLK+ CLK 10538-001AD9653 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation and Power-Down Mode ........................... 27 Applications ....................................................................................... 1 Digital Outputs and Timing ..................................................... 27 General Description ......................................................................... 1 Output Test Modes ..................................................................... 30 Functional Block Diagram .............................................................. 1 Serial Port Interface (SPI) .............................................................. 31 Product Highlights ........................................................................... 1 Configuration Using the SPI ..................................................... 31 Revision History ............................................................................... 3 Hardware Interface ..................................................................... 32 Specifications ..................................................................................... 4 Configuration Without the SPI ................................................ 32 DC Specifications ......................................................................... 4 SPI Accessible Features .............................................................. 32 AC Specifications .......................................................................... 6 Memory Map .................................................................................. 33 Digital Specifications ................................................................... 8 Reading the Memory Map Register Table ............................... 33 Switching Specifications .............................................................. 9 Memory Map Register Table ..................................................... 34 Timing Specifications ................................................................ 10 Memory Map Register Descriptions ........................................ 37 Absolute Maximum Ratings .......................................................... 12 Applications Information .............................................................. 39 Thermal Resistance .................................................................... 12 Design Guidelines ...................................................................... 39 ESD Caution ................................................................................ 12 Power and Ground Recommendations ................................... 39 Pin Configuration and Function Descriptions ........................... 13 Clock Stability Considerations ................................................. 39 Typical Performance Characteristics ........................................... 14 Exposed Pad Thermal Heat Slug Recommendations ............ 39 VREF = 1.0 V ................................................................................. 14 VCM ............................................................................................. 39 VREF = 1.3 V ................................................................................. 17 Reference Decoupling ................................................................ 39 Equivalent Circuits ......................................................................... 21 SPI Port ........................................................................................ 39 Theory of Operation ...................................................................... 22 Crosstalk Performance .............................................................. 40 Analog Input Considerations .................................................... 22 Outline Dimensions ....................................................................... 41 Voltage Reference ....................................................................... 23 Ordering Guide .......................................................................... 41 Clock Input Considerations ...................................................... 25 Rev. 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