Circuit Note CN-0371 Devices Connected/Referenced Synchronous Demodulator and ADA2200 Configurable Analog Filter Circuits from the Lab reference designs are engineered and 4.8 kHz, Ultralow Noise, 24-Bit AD7192 tested for quick and easy system integration to help solve todays Sigma-Delta ADC with PGA analog, mixed-signal, and RF design challenges. For more Low Voltage, 300 MHz, Quad 2:1 Mux information and/or support, visit www.analog.com/CN0371. ADG794 Analog HDTV Audio/Video Switch Ultralow Noise, 200 mA, CMOS ADP151 Linear Regulator Low Power LVDT Signal Conditioner with Synchronous Demodulation LVDTs utilize electromagnetic coupling between the movable core EVALUATION AND DESIGN SUPPORT and the coil assembly. This contactless (and hence frictionless) Circuit Evaluation Boards operation is a primary reason for why they are widely used in CN-0371 Circuit Evaluation Board (EVAL-CN0371-SDPZ) aerospace, process controls, robotics, nuclear, chemical plants, System Demonstration Platform (EVAL-SDP-CB1Z) hydraulics, power turbines, and other applications where Design and Integration Files operating environments can be hostile and long life and high Schematics, Layout Files, Bill of Materials reliability are required. CIRCUIT FUNCTION AND BENEFITS The entire circuit, including the LVDT excitation signal, consumes The circuit shown in Figure 1 is a complete linear variable only 10 mW of power. The circuit excitation frequency and output differential transformer (LVDT) signal conditioning circuit that data rates are SPI programmable. The system has a programmable can accurately measure linear position or linear displacement from bandwidth vs. dynamic range trade-off. It supports bandwidths a mechanical reference. Synchronous demodulation in the analog of over 1 kHz, and at a bandwidth of 20 Hz, the circuit has a domain is used to extract the position information and provides dynamic range of 100 dB, making it ideal for precision industrial immunity to external noise. A 24-bit, - analog-to-digital position and gauging applications. converter (ADC) digitizes the position output for high accuracy. 3.3V 5.0V 0.1F 3.3V 5.0V 0.1F E-100 SERIES LVDT 3.3V ADP151 3.3V VDD R34 0.1F INP ADG794 C24 0.1F ADA2200 R33 100 AV DV DD DD REFIN1(+) VOCM 2. 2k 0.01F DOUT C4 OUTP AIN1 100 R4 DIN AD7192 R35 2. 2k SCLK INN OUTN AIN2 C25 CS 0.01F 0.01F MCLK2 AGND DGND REFIN1() RCLK 4.8kHz GND CLKIN 4.92kHz Figure 1. LVDT Signal Conditioning Circuit (Simplified Schematic: All Connections and Decoupling Not Shown) Rev. 0 Circuits from the Lab reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. determining its suitability and applicability for your use and application. Accordingly, in no event shall Tel: 781.329.4700 www.analog.com Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due Fax: 781.461.3113 2015 Analog Devices, Inc. All rights reserved. to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) 13050-001CN-0371 Circuit Note the output data rate. To maintain the output bandwidth at the CIRCUIT DESCRIPTION maximum output date rate of 4.8 kHz, the output antialiasing The ADA2200 synchronous demodulator extracts position filter 3 dB corner frequency is set to approximately 2 kHz. For information by filtering the LVDT secondary signal before systems requiring lower output data rates, the antialiasing filter demodulating the signal to a low frequency output voltage that corner frequency can be reduced accordingly. is proportional to the LVDT core displacement. The ADA2200 drives the AD7192 24-bit - ADC, which digitizes and filters Integrated Synchronous Demodulator the output. The ADA2200 generates the synchronous LVDT The ADA2200 integrated synchronous demodulator forms the excitation signal, and the ADG794 switch converts the CMOS core of the circuit. It uses a unique charge sharing technology to level excitation signal into a precision 3.3 V square wave to perform discrete time signal processing in the analog domain. drive LVDT primary winding. The signal path of the ADA2200 is completely differential. It consists of a high impedance input buffer followed by a fixed The LVDT is an absolute displacement transducer that converts low-pass filter (FIR decimation filter), a programmable IIR a linear displacement into a proportional electrical signal. An filter, a demodulator, and a differential output buffer. It has an LVDT is a specially wound transformer with a moveable core input and output common-mode voltage equal of 1.65 V ( of that is affixed to the position to be measured. An excitation the 3.3 V supply voltage). signal is applied to the primary windings. As the core moves, the voltage on the secondary windings changes proportionally, The ADA2200 accepts the 4.92 MHz clock from the AD7192 and from this voltage, position is calculated. ADC and generates all of its internal clocking signals as well as the 4.8 kHz reference clock used as the LVDT excitation There are many types of LVDTs and different ways of extracting signal. The ADA2200 has configurable clock dividers that can position from them. The Figure 1 circuit uses the LVDT in 4-wire be programmed to support many different excitation mode. The two LVDT secondary outputs are connected such frequencies. that the voltages oppose each other, performing a subtraction. When the LVDT core is in its null position, the voltages on each CMOS Switch of the two secondaries are equal, and the voltage difference The ADG794 CMOS switch was chosen for the low on across the two windings is zero. As the core moves from the null resistance of the switches, fast switching times, break-before- position, the difference voltage across the secondary windings make switching action, and low cost. increases. The phase of the LVDT output voltage changes based The ADG794 converts the low voltage CMOS-level RCLK on direction. output of the ADA2200 into a low impedance differential The master clock for this circuit is generated by the AD7192 output square wave source, which drives the LVDT. To provide ADC. The ADA2200 accepts the master clock and generates headroom for the switches to drive the positive 3.3 V signal, all of its internal clocks, including the reference clock used as the ADG794 V input is supplied from the 5 V power supply. DD the LVDT excitation signal. The clock dividers on the ADA2200 LVDT are configured to provide an excitation signal of 4.8 kHz. The ADG794 converts the excitation signal to a precision 3.3 V The Figure 1 circuit supports a wide variety of LVDTs with square wave from the ADC supply voltage. The 3.3 V supply is minor modifications. The E-100 LVDT from Measurement also used as the ADC reference voltage therefore, the ratiometric Specialties, Inc., was used in 4-wire mode to demonstrate the relationship between the excitation signal and ADC reference main attributes of the circuit. The E-100 has a stroke range of voltage improves the noise and stability performance of the circuit. 2.54 mm, an output sensitivity of 240 mV/V at the stroke ends, The 3.3 V for the system is supplied by an ADP151 low dropout and a maximum linearity error of 0.5% of full-scale range. regulator driven from a 5 V supply. The operating frequency range is from 100 Hz to 10 kHz. See the E-Series LVDT data sheet for complete details. The coupling circuit between the LVDT secondary windings and the ADA2200 input is used to band limit the signal and ADA2200 Input Coupling Network to adjust the relative phase between the RCLK and ADA2200 The ADA2200 input coupling network can be tuned for input. The circuit is configured to maximize the quadrature different LVDTs. The inductance of the LVDT secondary (Phase = 90) response and to minimize the in-phase (Phase = 0) windings and the shunt capacitor (C4) form a tank circuit. response. This enables the position to be determined by only The R4 and R33 resistors reduce the Q of the tank circuit, measuring the quadrature output and makes the ADA2200 making the circuit less sensitive to changes in the LVDT output voltage less sensitive to phase variations in the circuit. winding inductance and resistance at the expense of increased The main sources of phase variation come from temperature power consumption. The pair of RC filters created by R34/C24 changes in the LVDT that cause its effective series resistance and R35/C25 reduces the signal bandwidth and provides and inductance to change. additional degrees of freedom for adjusting the relative phase of The antialiasing filter at the ADA2200 output maintains the the circuit. The maximum output from the ADA2200 internal signal bandwidth supported by the ADC. The output bandwidth phase sensitive detector (PSD) occurs at relative phase shifts of of the AD7192 internal digital filter is approximately 0.27 times 0 or 180. Rev. 0 Page 2 of 6