EVALUATION KIT AVAILABLE Click here for production status of specific part numbers. MAX22700DMAX22702D Ultra-High CMTI MAX22700EMAX22702E Isolated Gate Drivers General Description Benefits and Features Matching Propagation Delay The MAX22700MAX22702 are a family of single-chan- 20ns Minimum Pulse Width nel isolated gate drivers with ultra-high common-mode 35ns Propagation Delay at Room Temperature transient immunity (CMTI) of 300kV/s (typ). The devices 2ns Part-to-Part Propagation Delay Matching at are designed to drive silicon-carbide (SiC) or gallium- Room Temperature nitride (GaN) transistors in various inverter or motor 5ns Part-to-Part Propagation Delay Matching over control applications. All devices have integrated digital -40C to +125C Temperature Range galvanic isolation using Maxims proprietary process tech- nology. The devices feature variants with output options High CMTI (300kV/s, typ) for gate driver common pin GNDB (MAX22700), Miller Robust Galvanic Isolation clamp (MAX22701), and adjustable undervoltage-lockout Withstands 3kV for 60s (V ) RMS ISO UVLO (MAX22702). In addition, variants are offered as Continuously Withstands 848V (V ) RMS IOWM differential (D versions) or single-ended (E versions) Withstands 5kV Surge Between GNDA and V SSB inputs. These devices transfer digital signals between with 1.2/50s Waveform circuits with different power domains. All of the devices in Precision UVLO the family feature isolation for a withstand voltage rating Options to Support a Broad Range of Applications of 3kV for 60 seconds. RMS 3 Output Options: GNDB, Miller Clamp, or All devices support a minimum pulse width of 20ns with a Adjustable UVLO maximum pulse width distortion of 2ns. The part-to-part 2 Input Configurations: Single-Ended with Enable propagation delay is matched within 2ns (max) at +25C (E versions) or Differential (D versions) ambient temperature, and 5ns (max) over the -40C to +125C operating temperature range. This feature Applications reduces the power transistors dead time, thus improving Isolated Gate Driver for Inverters overall efficiency. Motor Drives The MAX22700 and the MAX22702 have a maximum UPS and PV Inverters R of 1.25 for the low-side driver, and the MAX22701 DSON has an R of 2.5 for the low-side driver. All devices DSON Safety Regulatory Approvals have a maximum R of 4.5 for the high-side driver. DSON UL According to UL1577 See the Ordering Information for suffixes associated with each option. cUL According to CSA Bulletin 5A The MAX22700MAX22702 can be used to drive SiC or GaN FETs with different output gate drive circuitry and B-side supply voltages. See the Typical Operating Circuits Ordering Information appears at end of data sheet. for details. All of the devices in the MAX22700MAX22702 family are available in an 8-pin, narrow-body SOIC package with 4mm of creepage and clearance. The package material has a minimum comparative tracking index (CTI) of 600V, which gives it a group I rating in creepage tables. All devices are rated for operation at ambient temperatures of -40C to +125C. 19-100581 Rev 3 1/20MAX22700DMAX22702D Ultra-High CMTI MAX22700EMAX22702E Isolated Gate Drivers Absolute Maximum Ratings V to GNDA ........................................................-0.3V to +6V OUT to V ..........................................-0.3V to (V + 0.3V) DDA SSB DDB V to GNDB ......................................................-0.3V to +40V Continuous Power Dissipation (T = +70C) DDB A GNDB to V ......................................................-0.3V to +40V Narrow SOIC (derate 9.39mW/C above +70C) ......750.89mW SSB V to V .......................................................-0.3V to +40V Operating Temperature Range ......................... -40C to +125C DDB SSB INP, INN, IN, EN to GNDA.......................................-0.3V to +6V Maximum Junction Temperature .....................................+150C V to ADJ ............................................................-0.3V to +6V Storage Temperature Range ............................ -60C to +150C DDB CLAMP to V .....................................-0.3V to (V + 0.3V) Soldering Temperature (reflow) .......................................+260C SSB DDB Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information PACKAGE TYPE: 8 NARROW SOIC Package Code S8MS+23 Outline Number 21-0041 Land Pattern Number 90-0096 THERMAL RESISTANCE, FOUR-LAYER BOARD Junction to Ambient ( ) 106.54C/W JA Junction to Case ( ) 44.91C/W JC For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a +, , or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. DC Electrical Characteristics (V - V = 5V, V - V = 20V, V = V = 0V, T = -40C to +125C, unless otherwise noted. Typical values are at DDA GNDA DDB SSB GNDA SSB A T = +25C, unless otherwise noted.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY V Relative to GNDA 3 5.5 DDA Relative to GNDB, MAX22700 13 36 Supply Voltage V Relative to V , MAX22701 13 36 DDB SSB V Relative to V , MAX22702 6 36 SSB V Relative to GNDB, MAX22700 -16 0 SSB Differential Supply V V - V , MAX22700 13 36 DIFF DDB SSB V V rising 2.69 2.82 2.95 V Undervoltage-Lockout UVLOAP DDA Threshold V V falling 2.59 2.72 2.85 V UVLOAN DDA Undervoltage-Lockout V 100 mV UVLOA HYST Threshold Hysteresis Maxim Integrated 2 www.maximintegrated.com