APS12808L-OBMRC AP Memory

APS12808L-OBMx DDR OPI Xccela PSRAM Double-Data-Rate Octal SPI PSRAM Specifications Features Single Supply Voltage Low Power Features o VDD=1.62 to 1.98V o Partial Array Self-Refresh (PASR) o VDDQ=1.62 to 1.98V o Auto Temperature Compensated Self- Refresh (ATCSR) by built-in temperature Interface: Octal SPI with DDR Xccela mode, two bytes transfers per one clock cycle sensor o User configurable refresh rate Performance: Clock rate up to 200MHz, o Ultra Low Power (ULP) Half Sleep mode 400MB/s read/write throughput with data retained Organization: 128Mb, 16M x 8bits with 1024 Software Reset bytes page size Reset Pin Available o Column address: AY0 to AY9 o Row address: AX0 to AX13 Output Driver LVCMOS with programmable Refresh: Self-managed drive strength Data Mask (DM) for write data Operating Temperature Range o Tc = -40C to +85C (standard range) Data Strobe (DQS) enabled highspeed read o Tc = -40C to +105C (extended range) operation Maximum Standby Current Register Configurable write and read initial o 600A 105C latencies o 400A 85C Write Burst Length, maximum 1024 bytes, o 200A 25C minimum 2 bytes o 60A 25C (Half Sleep Mode with data Wrap & Hybrid Burst in 16/32/64/1K lengths retained) Linear Burst Command Row Boundary Crossing (RBX) o read operations can be enabled via Mode Register. o RBX Write is NOT supported o RA 13 Boundary Crossing is NOT supported between 2 dies APM Octal PSRAM Datasheet.pdf - Rev. 3.0a Dec 11, 2019 1 of 28 AP Memory reserves the right to change products and/or specifications without notice 2019 AP Memory. All rights reserved APS12808L-OBMx DDR OPI Xccela PSRAM Table of Contents 1 Table of Contents 1 Table of Contents ............................................................................................................. 2 2 Package Information ........................................................................................................ 3 3 Package Outline Drawing ................................................................................................. 4 4 Ordering Information ....................................................................................................... 5 5 Signal Table ...................................................................................................................... 6 6 Power-Up Initialization .................................................................................................... 7 6.1 Power-Up Initialization Method 1 (via. RESET pin) ............................................... 7 6.2 Power-Up Initialization (via. Global Reset) ............................................................. 8 7 Interface Description ....................................................................................................... 9 7.1 Address Space ......................................................................................................... 9 7.2 Burst Type & Length ................................................................................................ 9 7.3 Command/Address Latching ................................................................................... 9 7.4 Command Truth Table ............................................................................................ 9 7.5 Read Operation ..................................................................................................... 10 7.6 Write Operation .................................................................................................... 13 7.7 Control Registers ................................................................................................... 14 7.8 Half Sleep Mode .................................................................................................... 20 7.9 Deep Power Down Mode ...................................................................................... 21 8 Electrical Specifications: ................................................................................................ 22 8.1 Absolute Maximum Ratings .................................................................................. 22 8.2 Pin Capacitance ..................................................................................................... 22 8.3 Decoupling Capacitor Requirement ...................................................................... 23 8.4 Operating Conditions ............................................................................................ 23 8.5 DC Characteristics ................................................................................................. 24 8.6 I SB Partial Array Refresh Current ......................................................................... 25 8.7 AC Characteristics ................................................................................................. 26 9 Change Log ..................................................................................................................... 28 APM Octal PSRAM Datasheet.pdf - Rev. 3.0a Dec 11, 2019 2 of 28 AP Memory reserves the right to change products and/or specifications without notice 2019 AP Memory. All rights reserved