AP72200 HIGH EFFICIENCY SYNCHRONOUS DC-DC BUCK-BOOST CONVERTER WITH 4.3A SWITCHES Description Pin Assignments The AP72200 is a high-current synchronous buck-boost converter providing high efficiency, excellent transient response, and high DC output accuracy. The targeted applications are smartphones, tablets, and other handheld devices. The AP72200 utilizes a four-switch H- bridge configuration to support buck and boost operation. The buck- boost provides at least 2A output current. The current control scheme handles wide input/output voltage ratios and provides low external component count with outstanding performance in line/load transient response and seamless transition between buck and boost modes. 2 The AP72200 features I C compatible, two-wire serial interface consisting of a bidirectional serial-data line, SDA, and a serial-clock line, SCL. It supports SCL clock rates up to 3.4MHz. The AP72200 also features UVLO, OTP, and OCP to protect the TOP VIEW circuit. (BALLS SIDE DOWN) This IC is available in a small 2.125mm 1.750mm, 20 balls WLCSP package. Features Applications V 2.3V to 5.5V IN Smartphones Output Voltage Range: 2.6V to 5.14V Tablets 2A Continuous Output Current for V =3.4V and V >2.9V OUT IN Portable Consumer Devices Efficiency Up to 97% 2.5MHz Switching Frequency 2 I C Interface Selectable MODE PFM/PWM 2 Ultrasonic Operation Programmable through I C Power Good Indicator with 5M Internal Pull-Up Adjustable Overcurrent Limit Fully Protected for Overcurrent, Short Circuit, Reverse Current Protection, Overtemperature, and UVLO Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. Green Device (Note 3) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See AP72200 Typical Applications Circuit VIN = 2.3V to 5.5V PVIN SW1 L1 C1 1H 10F SW2 EN VOUT VIN VOUT OCP C2 2x22F FB VIO PG SCL MODE SDA GND PGND Figure 1 Typical Application Circuit Pin Descriptions Pin Number Pin Function Name 20 BALLS VIN A1 Input supply for the logic control circuitries. OCP program the current limit. LOW will set the OCP threshold to 2A. HIGH will set the OCP threshold to 4.3A. OCP A2 2 I C can override the MODE pin. See the register for more detail. MODE logic input. LOW for PFM operation. HIGH for forced PWM. MODE A3 There is an internal 5.5M resistor from MODE and GND to set the IC in PFM if left floating. 2 I C can override the MODE pin. See the register for more detail. 2 SDA A4 I C Data I/O. 2 SCL A5 I C Clock Input. FB B1 Feedback Input. FB senses the output voltage and regulates it. Connect FB to VOUT. Open drain power-good output that is pulled to GND when the output voltage is out of its regulation limits or PG B2 during soft-start interval. Active high by default. There is an internal 5M pull-up resistor to VIO. GND B3 Analog ground that is used for control. Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator low to EN B4 turn it off. 2 VIO B5 Input supply for the I C and PG internal pull-up resistor. VOUT C1, D1 Buck-Boost output. SW2 C2, D2 Switch Node 2. PGND C3, D3 Power Ground. SW1 C4, D4 Switch Node 1. Power Input. Bypass PVIN to GND with a 10F capacitor to eliminate noise on the input to the IC. See Input PVIN C5, D5 Capacitor. 2 of 30 July 2018 AP72200 Diodes Incorporated www.diodes.com Document number: DS40869 Rev. 3 - 2