PI6C49003 Networking Clock Generator Features Description The PI6C49003 is a clock generator device intended for PCIe/ 3.3V +/-10% Supply Voltage networking applications. The device includes ve 100MHz Uses 25MHz xtal such as Saronix-eCera SRX7278 differential Host Clock Signal Level (HCSL) outputs for PCIe, Five PCIe 100MHz outputs with optional -0.5% spread two single-ended 50 MHz outputs, one single-ended 32.256MHz spectrum support output, and one selectable single-ended 33/66/133 MHz output. Two LVCMOS 50MHz outputs that support +/- 10% Using a serially programmable SMBUS interface, the PI6C49003 frequency margining incorporates spread spectrum modulation on the ve 100 MHz One frequency selectable 33/66/133MHz LVCMOS output HCSL PCIe outputs, and independent frequency margining on the One 32.256MHz LVCMOS output 50MHz output, 33.3333MHz and 66.6666MHz clock outputs. Industrial temperature -40C to 85C Package: 48-pin TSSOP package Pin Con guration 1 48 VDD GND IREF 2 47 VDD 3 46 NC 100M Q0- 4 45 NC 100M Q0+ 44 5 VDD 100M Q1+ 43 VDD 6 100M Q1- 42 GND 7 VDD 8 41 GND GND 9 40 VDD VDD Block Diagram 10 39 GND 100M Q2+ VDD 38 11 VDD 100M Q2- 14 37 SCLK 12 100M Q3+ 36 SDATA 13 100M Q3- 25 MHz Clock Buffer/ 14 35 crystal or GND VDD Crystal 5 clock input Oscillator 100M OUT(0-4) 15 34 50M Out1 GND 16 33 50M Out2 VDD 50M OUT(1-2) 32 VDD 17 100M Q4+ PLL, Dividers, Buffers, and 31 GND 18 100M Q4- Logic 33/66/133M OUT1 19 30 VDD 33/66/133M Out1 32.256M Out1 20 29 SCLK VDD 32.256M OUT1 SDATA GND 21 28 GND PD RESET NC 22 27 VDD NC 23 26 X2 PD RESET 24 25 X1 10 ISET 475 Ohms GND 1% PS9023A 11/20/09 09-0097 1PI6C49003 Networking Clock Generator Pin Description Pin Pin Name Pin Type Pin Description 1V Power 3.3V Supply Pin DD 2 IREF Output Connect to 475-Ohm resistor to set HCSL output drive current 3 NC No connect. Leave open 4 NC No connect. Leave open 5V Power 3.3V Supply Pin DD 6V Power 3.3V Supply Pin DD 7 GND Power Ground 8 GND Power Ground 9V Power 3.3V Supply Pin DD 10 GND Power Ground 11 V Power 3.3V Supply Pin DD 12 SCLK Input SMBus compatible input clock. Supports fast mode 400kHz input clock. 13 SDATA I/O SMBus compatible data line 14 GND Power Ground 50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110k- 15 50M Out1 Output Ohm pull-down. 50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110k- 16 50M Out2 Output Ohm pull-down. 17 V Power 3.3V Supply Pin DD 18 GND Power Ground 19 V Power 3.3V Supply Pin DD 32.256MHz LVCMOS output. When disabled, output is trisated and has a nominal 20 32.256M Out1 Output 110k-Ohm pull-down. 21 GND Power Ground 22 NC 23 NC Power down reset - when low all PLL s are powered down and outputs tristated. 24 PD RESET Input SMBus registers are reset to default values. 25 X1 Input Crystal input. Integrated 6pF capacitance 26 X2 Output Crystal output. Integrated 6pF capacitance 27 V Power 3.3V Supply Pin DD 28 GND Power Ground 29 V Power 3.3V Supply Pin DD 33/66/133MHz selectable LVCMOS output. When disabled, output is trisated and has 30 33/66/133M Out1 Output a nominal 110k-Ohm pull-down. 31 100M Q4- Output 100MHz HCSL output 32 100M Q4+ Output 100MHz HCSL output 33 V Power 3.3V Supply Pin DD 34 GND Power Ground 35 V Power 3.3V Supply Pin DD (Continued) PS9023A 11/20/09 09-0097 2