PI6C557-03 PCI Express Clock Product Features Description LVDS compatible outputs e PTh I6C557-03 is a spread spectrum clock generator supporting PCI Express and Ethernet requirements. The device Supply voltage of 3.3V 10% is used for PC or embedded systems to substantially reduce 25MHz input frequency Electromagnetic Interference (EMI). HCSL outputs, 0.7V Current mode differential pair e PTh I6C557-03 provides two differential (HCSL) spread spectrum Jitter 60ps cycle-to-cycle (typ) outputs. The PI6C557-03 is configured to select spread and clock selection. Using Pericom s patented Phase-Locked Loop (PLL) Spread of 0.25%, -0.5%, -0.75%, and no spread techniques, the device takes a 25MHz crystal input and produces Industrial temperature range two pairs of differential outputs (HCSL) at 25MHz, 100MHz, Packaging: (Pb-free and Green) 125MHz and 200MHz clock frequencies. It also provides spread 16-pin, 173 mils wide TSSOP selection of 0.25%, -0.5%, -0.75%, and no spread. Block Diagram VDD 2 SS1:SS0 CLK0 2 Control CLK0 Logic S1:S0 2 Phase Lock Loop CLK1 X1/CLK CLK1 Crystal 25 MHz Driver crystal or clock X2 2 Pulling R R Capacitors GND OE Pin Configuration 1 S0 16 VDDX 2 S1 15 CLK0 3 SS0 14 CLK0 4 X1/CLK 13 GNDA X2 5 12 VDDA 6 OE 11 CLK1 GNDX 7 10 CLK1 8 SS1 9 IREF www.pericom.com 01/04/13 1 12-0307PI6C557-03 PCI Express Clock Pin Description Pin Pin Name I/O Type Description 1 S0 Input Select pin 0 (Internal pull-up resistor). See Table 1. 2 S1 Input Select pin 1 (Internal pull-up resistor). See Table 1. 3 SS0 Input Spread Select pin 0 (Internal pull-up resistor). See Table 2. 4 X1/CLK Input Crystal or clock input. Connect to a 25MHz crystal or single ended clock. 5 X2 Output Crystal connection. Leave unconnected for clock input. 6 OE Input Output enable. Internal pull-up resistor. 7 GNDX Power Crystal ground pin. 8 SS1 Input Spread Select pin 1 (Internal pull-up resistor). See Table 2. 9 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 10 CLK1 Output HCSL compliment clock output 11 CLK1 Output HCSL clock output 12 VDDA Power Connect to a +3.3V source. 13 GNDA Power Output and analog circuit ground. 14 CLK0 Output HCSL compliment clock output 15 CLK0 Output HCSL clock output 16 VDDX Power Connect to a +3.3V source. Table 1: Output Select Table Table 2: Spread Selection Table S1 S0 CLK(MHz) SS1 SS0 Spread 0 0 25 0 0 Center 0.25 0 1 100 0 1 Down -0.5 1 0 125 1 0 Down -0.75 1 1 200 1 1 No Spread www.pericom.com 01/04/13 2 12-0307