A product Line of Pb Diodes Incorporated Lead-free Green PI6CG18801 Very Low Power 8-Output PCIe Clock Generator With On-chip Termination Features Description 1.8V Supply Voltage e PTh I6CG18801 is an 8-output very low power PCIe Gen1/Gen2/ Gen3/ Gen4 clock generator. It uses 25MHz crystal or CMOS Crystal/CMOS input: 25 MHz reference as an input to generate the 100MHz low power 8 Differential low power HCSL outputs with on-chip differential HCSL outputs with on-chip terminations. The on-chip termination termination can save 32 external resistors and make layout easier. Individual output enable An additional buffered reference output is provided to serve as a Reference CMOS output low noise reference for other circuitry. Programmable slew rate and output amplitude for each output It uses Diodes proprietary PLL design to achieve very low Differential outputs blocked until PLL is locked jitter that meets PCIe Gen1/Gen2/Gen3/ Gen4 requirements. It also Selectable 0%, -0.25% or -0.5% spread on differential outputs provides various options such as different slew rate and amplitude through strapping pins or SMBUS so that users can configure the Strapping pins or SMBus for configuration device easily to get the optimized performance for their individual 3.3V Tolerant SMBus interface support boards. The device also supports selectable spread-spectrum Very low jitter outputs options to reduce EMI for various applications. Differential cycle-to-cycle jitter <50ps Differential output-to-output skew <60ps Block Diagram PCIe Gen1/Gen2/Gen3/ Gen4 compliant CMOS REFOUT phase jitter is < 1.5ps RMS REFOUT OE 5:0 Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Q7 Halogen and Antimony Free. Green Device (Note 3) Q6 For automotive applications requiring specic cfi hange control XTAL IN/CLK OSC PLL XTAL OUT (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, SS Q3 and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. SCLK Q4 SDATA SADR A product Line of Diodes Incorporated PI6CG18801 Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 1 36 Q5- SS SEL TRI GND XTAL 2 35 Q5+ 3 34 OE4 XTAL IN/CLK XTAL OUT 4 33 Q4- V 5 32 Q4+ DD OSC 6 V O V 31 DD DD REFOUT GND 7 30 VDDA SADR/REFOUT 8 GNDA GND REFOUT 29 9 OE3 GND DIG 28 10 Q3- SCLK 27 11 SDATA 26 Q3+ 12 V 25 OE2 DD DIG 13 14 15 16 17 18 19 20 21 22 23 24 Pin Description Pin Pin Name Type Description Latched select input to select spread spectrum amount at initial power up 1 SS SEL TRI Input Tri-level 1 = -0.5% spread, M = -0.25%, 0 = Spread Off 2 GND XTAL Power Ground for oscillator circuit 3 XTAL IN/CLK Input Crystal input or CMOS reference input 4 XTAL OUT Output Crystal output 5 V OSC Power Power supply for oscillator circuitry, nominal 1.8V DD 6 V REFOUT Power Power supply for buffered CMOS output DD Input/ Latch to select SMBus Address or 1.8V LVCMOS REFOUT. 7 SADR/REFOUT CMOS Output This pin has an internal pull-down 8 GND REFOUT Power Ground for REFOUT 9 GND DIG Power Ground for digital circuitry 10 SCLK Input CMOS SMBUS clock input, 3.3V tolerant Input/ 11 SDATA CMOS SMBUS Data line, 3.3V tolerant Output 12 V DIG Power Power supply for digital circuitry, nominal 1.8V DD 13, 21, 31, V Power Power supply for differential outputs DDO 39, 47 Active low input for enabling Q0 pair. This pin has an internal pull-down. 14 OE0 Input CMOS 1 =disable outputs, 0 = enable outputs www.diodes.com July 2020 PI6CG18801 2 Diodes Incorporated Document Number DS39994 Rev 6-2 V O DD PD OE0 V O DD Q0+ OE7 Q0- Q7- OE1 Q7+ Q1+ OE6 Q1- Q6- VDD Q6+ GND V O DD V O DD GND V DD Q2+ OE5 Q2-