PI6LC48H02-01LIE Diodes Incorporated

PI6LC48H02-01 PCIe 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs Features Description PCIe 3.0/2.0/1.0 compliant e PTh I6LC48H02-01 is a clock generator compliant to PCI Ex - press 3.0/2.0/1.0 and Ethernet requirements. The device is used PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.) for servers, networking or embedded systems. LVDS compatible outputs Supply voltage of 3.3V 10% e PTh I6LC48H02-01 provides two differential (HCSL) or LVDS 25MHz crystal or clock input frequency outputs. Using Pericom s patented Phase Locked Loop (PLL) HCSL outputs, 0.8V Current mode differential pair techniques, the device takes a 25MHz crystal input and produces Jitter 35ps cycle-to-cycle (typ) two pairs of differential outputs (HCSL) at 25MHz, 100MHz, 125MHz, 200MHz clock frequencies. RMS phase jitter 12kHz ~ 20MHz 100MHz - 0.32ps (typ) RMS phase jitter 12kHz ~ 20MHz 125MHz - 0.3ps (typ) Power down mode Industrial temperature range Packaging: (Pb-free and Green): 16-pin TSSOP (L16) Block Diagram Pin Configuration (16-Pin TSSOP) VDD 16 S0 1 VDDX CLK0 15 Control S1 2 CLK0 CLK0 Logic S1:S0 Phase 14 PD 3 CLK0 2 Lock Loop 13 X1/CLK 4 GNDA CLK1 X1/CLK 12 X2 5 VDDA CLK1 Crystal 25 MHz 11 Driver OE 6 CLK1 crystal or clock X2 10 GND 7 CLK1 Pulling R R 9 NC 8 IREF Capacitors PD GND OE All trademarks are property of their respective owners. www.pericom.com PI6LC48H02-01 Rev B 09/23/2015 15-0125 1PI6LC48H02-01 PCIe 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs Pin Description Pin Pin Name I/O Type Description 1 S0 Input Select pin 0 (Internal pull-up resistor). See Table 1. 2 S1 Input Select pin 1 (Internal pull-up resistor). See Table 1. 3 PD Input Power down mode. Internla pull-up resistor. See Table 2. 4 X1/CLK Input Crystal or clock input. Connect to a 25MHz crystal or single ended clock. 5 X2 Output Crystal connection. Leave unconnected for clock input. 6 OE Input Output enable. Internal pull-up resistor. 7 GND Power Ground 8 NC - Do not connect 9 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 10 CLK1 Output HCSL compliment clock output 11 CLK1 Output HCSL clock output 12 VDDA Power Connect to a +3.3V source. 13 GNDA Power Output and analog circuit ground. 14 CLK0 Output HCSL compliment clock output 15 CLK0 Output HCSL clock output 16 VDDX Power Connect to a +3.3V source. Table 1: Output Select Table S1 S0 CLK(MHz) 0 0 25 0 1 100 1 0 125 1 1 200 Table 2: Power down mode PD Device 0 Power down mode 1 Normal Operation mode, default All trademarks are property of their respective owners. www.pericom.com PI6LC48H02-01 Rev B 09/23/2015 15-0125 2