PI6LC48H04
PCIe 3.0 and Ethernet Clock Generator with 4 HCSL Outputs
Features Description
PCIe 3.0/2.0/1.0 compliant e PTh I6LC48H04 is a clock generator compliant to PCI Express
3.0/2.0/1.0, Ethernet and other requirements. The device is used
PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.)
for networking or embedded systems.
LVDS compatible outputs
e PTh I6LC48H04 provides four differential (Low Power HCSL)
Supply voltage of 3.3V5% and 2.5V5%
or LVDS outputs. Using Pericom's patented Phase Locked Loop
25MHz crystal or clock input frequency
(PLL) techniques, the device takes a 25MHz crystal input and
HCSL outputs, 0.7V low power differential pair
produces four pairs of differential outputs (HCSL) at 156.25MHz,
100MHz, 125MHz, 133.33MHz and 200MHz clock frequencies.
Jitter 35ps cycle-to-cycle (typ)
RMS phase jitter 12kHz ~ 20MHz @ 100MHz - 0.32ps (typ)
RMS phase jitter 12kHz ~ 20MHz @ 125MHz, 156.25MHz,
200MHz - 0.3ps (typ)
Industrial temperature range
Packaging: (Pb-free and Green)
20-pin TSSOP (L20)
Block Diagram Pin Configuration (20-Pin TSSOP)
VDDX VDDOA
1
VDDX 20 Q0+
OE0&1
2
19
OE0&1 Q0-
Q0+ 3
18
S0 Q1+
Control
Q0-
4
17
Logic S1 Q1-
S[1:0] Q1+
Phase
2
5
16
XTAL_IN/ CLK GNDOA
Lock
Q1-
Loop
Q2+
6
15
XTAL_OUT VDDOA
Q2-
7
XTAL_IN/CLK 14
PD# Q2+
Q3+
Crystal
25 MHz 8
13
Q3- OE Q2-
Driver
crystal or clock
OE
XTAL_OUT
9
GNDX 12 Q3+
10
VSwing_Ctrl 11 Q3-
Pulling
Capacitors
VSWING_CTRL
GNDX GNDOA
All trademarks are property of their respective owners. www.pericom.com PI6LC48H04 Rev.A 04/07/2015
15-0047 1PI6LC48H04
PCIe 3.0 and Ethernet Clock Generator with 4 HCSL Outputs
Pin Description
Pin # Pin Name I/O Type Description
1 VDDX Power Crystal supply pin.
Output enable pin for Q0+/- and Q1+/-. When HIGH, output is enabled
2 OE0&1 Input Pull-up and active. When LOW, output is disabled and in high impedance state.
Dont care if OE is LOW. Internal 343kpull-up resistor.
3 S0 Input Pull-up Frequency select pin. Internal 343k pull-up resistor.
4 S1 Input Pull-up Frequency select pin. Internal 343k pull-up resistor.
Crystal or clock input. Connect to a 25MHz crystal or single ended
5 XTAL_IN/CLK Input
clock.
6 XTAL_OUT Output Crystal output. Leave unconnected for clock input.
Power down pin. When HIGH, the device is in normal operation. When
7 PD# Input Pull-up LOW, the device is in power down mode and all outputs are in high
impedance state. Internal 343k pull-up resistor.
Output enable pin for all outputs. When HIGH, Q2+/- and Q3+/- are en-
abled and active and Q0+/- and Q1+/- depends on OE0&1. When LOW,
8 OE Input Pull-up
all outputs are disabled and in high impedance state and not dependent
on OE0&1. Internal 343k pull-up resistor.
9 GNDX Power Crystal ground.
VSWING_ Pull-up and VOH selection pin for all outputs. Tri-level selction for different voltage
10 Input
CTRL pull down swings.
11,12 Q3-, Q3+ Output Low power HCSL clock output 3.
13,14 Q2-, Q2+ Output Low power HCSL clock output 2.
15 VDDOA Power Analog and output supply pin.
16 GNDOA Power Analog and output ground.
17,18 Q1-, Q1+ Output Low power HCSL clock output 1.
19,20 Q0-, Q0+ Output Low power HCSL clock output 0.
Table 1: Output Select Table (25MHz Xtal Input)
Table 1a: Output Select Table (Generating other frequencies)
S1 S0 CLK(MHz) Xtal Input Freq. S1 S0 CLK(MHz)
0 0 156.25
21.33MHz 0 0 133.3MHz
0 1 100 26.66MHz 1 0 133.3MHz
1 0 125
Note: Above frequencies are only for the provided settings. Do
1 1 200 (Default) not deviate from provided S1, S0 settings. For any other output
frequencies, please contact Pericom
Table 2: Output Enable Table
OE OE0&1 Q0+/- Q1+/- Q2+/- Q3+/-
0 0 HiZ HiZ HiZ HiZ
0 1 HiZ HiZ HiZ HiZ
1 0 HiZ HiZ Active Active
1 (Default) 1 (Default) Active Active Active Active
All trademarks are property of their respective owners. www.pericom.com PI6LC48H04 Rev.A 04/07/2015
15-0047 2