PI6LC48P0301 3-Output LVPECL Networking Clock Generator Features Description Three differential LVPECL output pairs e PTh I6LC48P0301 is a 3-output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies and is a mem- Selectable crystal oscillator interface or LVCMOS/LVTTL ber of Pericoms HiFlex family of high performance clock solu- single-ended clock input tions. Using a 19.53125MHz or 25MHz crystal, the most popular Supports the following output frequencies: 125MHz, Ethernet frequencies can be generated based on the settings of 4 156.25MHz, 312.5MHz, 625MHz frequency select pins. RMS phase jitter 156.25MHz, using a 25MHz crystal e PTh I6LC48P0301 uses Pericoms proprietary low phase noise (1.875MHz 20MHz): 0.16ps (typical) PLL technology to achieve ultra low phase jitter, so it is ideal for RMS phase jitter 156.25MHz, using a 25MHz crystal Ethernet interface in all kind of systems. (12kHz 20MHz): 0.32ps (typical) PI6C20800B Full 3.3V or 2.5V supply modes Commercial and industrial ambient operating temperature Available in lead-free package: 24-TSSOP Applications Networking systems Block Diagram NA SEL 0:1 OEA CLKA /A CLKA XTAL IN OEB OSC PFD VCO XTAL OUT CLKB0 /B CLKB0 Ref IN CLKB1 M CLKB1 IN SEL PLL ByPass FBN NB SEL 0:1 M reset www.pericom.com PI6LC48P0301 Rev. A 07/30/13 13-0116 1PI6LC48P0301 3-Output LVPECL Networking Clock Generator Pin Configuration NB SEL0 24 1 NB SEL1 PLL ByPass 23 VDDOB 2 M reset 22 3 CLKB0 VDDOA 4 21 CLKB0 CLKA 5 20 CLKB1 CLKA 6 19 CLKB1 18 OEB 7 IN SEL 17 OEA 8 Ref IN FBN 9 16 XTAL IN 15 VDDA 10 XTAL OUT VDD 11 14 GND 13 NA SEL0 12 NA SEL1 Pinout Table Pin No. Pin Name I/O Type Description NB SEL0, 1, 24 Input Pull-up Bank B Output Divider Select NB SEL1 2 PLL ByPass Input Pull-up Active Low PLL Bypass Master Reset. When HIGH, CLKx goes to low and CLKx goes to 3 M reset Input Pull-down high When LOW outputs are enabled. 4 VDDOA Power Bank A Output Power Supply 5, CLKA, Output Bank A LVPECL Output Clock 6 CLKA 7 OEB Input Pull-up Bank B Output Enable. When LOW, output is differential low. 8 OEA Input Pull-up Bank A Output Enable. When LOW, output is differential low. 9 FBN Input Pull-down Feedback Divider Select 10 VDDA Power Analog Power Supply 11 VDD Power Core Power Supply 12, NA SEL0, Input Pull-up Bank A Output Divider Select 13 NA SEL1 14 GND Ground Ground XTAL OUT, 15, 16 Crystal Crystal Input and Output XTAL IN 17 Ref IN Input Pull-down CMOS Reference Clock Input When HIGH, Crystal is selected When LOW, reference input is 18 IN SEL Input Pull-up selected. 19, CLKB1 , Output Bank B LVPECL Output Clock 1 20 CLKB1 CLKB0 , 21, 22 Output Bank B LVPECL Output Clock 0 CLKB0 23 VDDOB Power Bank B Output Power Supply www.pericom.com PI6LC48P0301 Rev. A 07/30/13 13-0116 2