FUJITSU SEMICONDUCTOR FACT SHEET NP501-00020-2v0-E FRAM MB85RC64A 2 MB85RC64A is a 64K-bits FRAM LSI with serial interface (I C), using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, etc. FEATURES Bit configuration 8,192 words 8 bits Two-wire serial interface : Fully controllable by two ports: serial clock(SCL) and serial data(SDA) Operating frequency :1 MHz (Max) 12 Read/write endurance :10 times / byte Data retention :10 years (+ 85 ), 95 years (+ 55 ), over 200 years (+ 35 ) Operating power supply voltage 2.7V to 3.6V Low power consumption Operating power supply current 250A (Typ1MHz) Standby current 5A (Typ) Operating ambient temperature range-40 to +85 Package 8-pin plastic SOP (FPT-8P-M02) RoHS compliant ORDERING INFORMATION Product name Package Shipping form 8-pin plastic SOP MB85RC64APNF-G-JNE1 (FPT-8P-M02) Tube 3.90mm5.05mm,1.27mm pitch 8-pin plastic SOP MB85RC64APNF-G-JNERE1 (FPT-8P-M02) Embossed Carrier tape 3.90mm5.05mm,1.27mm pitch PACKAGE EXAMPLE OF REFERENCE 8-pin plastic SOP (FPT-8P-M02) May 2013 1/2 Copyright2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB85RC64A PIN ASSIGNMENT (TOP VIEW) Pin No. Pin name Description Device Address pins MB85RC64 can be connected to the same data bus up to 8 devices. Device addresses A0 1 8 VDD are used in order to identify each of the devices. Connect these pins to VDD 1 to 3 A0 to A2 pin or VSS pin externally. Only if the combination of VDD and VSS pin matches a Device Address Code inputted from the SDA pin, the device operates. In the 2 7 A1 WP open pin state, A0, A1, and A2 pins are internally pulled-down and recognized as the level. 4 VSS Ground pin A2 3 6 SCL Serial Data I/O pin This is an I/O pin which performs bidirectional communication for both memory 5 SDA address and writing/reading data. It is possible to connect multiple devices. It is an open drain output so a pull-up resistor is required to be connected VSS 4 5 SDA to the external circuit. Serial Clock pin 6 SCL This is a clock input pin for input/output timing serial data. Data is sampled on the rising edge of the clock and output on the falling edge. Write Protect pin When the Write Protect pin is the level, the writing operation is disabled. When the Write Protect pin is the level, the entire memory region can be 7 WP overwritten. The reading operation is always enabled regardless of the Write Protect pin input level. The write protect pin is internally pull-down to VSS pin, and that is recognized as the level (write enable) when the pin is the open state. Supply Voltage pin 8 VDD BLOCK DIAGRAM Serial/Parallel Converter SDA FRAM Array 8,192 8 SCL WP Column Decoder/Sense Amp./ Write Amp. A0, A1, A2 2 I C 2 MB85RC64A has a two-wire serial interface the I C bus, and operates as a slave device. 2 The I C bus defines communication roles ofmaste andslav devices, with the master side holding the authority to initiate control. Furthermore, 2 an I C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a unique device address to the slave device, the master side starts communication after specifying the slave to communicate by addresses. NP501-00020-2v0-E May 2013 2/2 Copyright2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved Control Logic Address Counter Row Decoder