CY26121KZXI-21

CY26121 PacketClock Spread Spectrum Clock Generator PacketClock Spread Spectrum Clock Generator Features Benefits Integrated phase-locked loop (PLL) High-performance PLL tailored for spread spectrum application Low jitter, high-accuracy outputs Meets critical timing requirements in complex system designs 3.3 V operation Enables application compatibility 25 MHz input frequency Works with commonly available crystal or driven reference 33.33 MHz or 25 MHz selectable output frequency (-21) Downspread spread spectrum with 30 kHz nominal modulation frequency Functional Description For a complete list of related resources, click here. Frequency Table for CLKA-D Part Number CLKSEL = 0 CLKSEL = 1 Spread% Parallel Crystal Load CY26121-21 33.33 MHz 25.00 2.8% 15 pF Logic Block Diagram Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07350 Rev. *E Revised May 20, 2016CY26121 Pin Configuration Figure 1. 16-pin TSSOP pinout XIN 1 16 XOUT V 2 15 NC DD 3 14 AVDD REF 13 CLKSEL 4 VSS 12 AVSS 5 CLKD 11 VSSL 6 VDDL 10 CLKA 7 SSON 9 CLKC 8 CLKB Pin Definitions Pin Name Pin Number Description XIN 1 Reference input Or crystal input VDD 2 3.3 V voltage supply AVDD 3 3.3 V analog voltage CLKSEL 4 (-21) 0 = 33.33 MHz out, 1 = 25 MHz Out. Weak pull-up. AVSS 5 Analog ground VSSL 6 CLK ground CLK(A:D) 7, 8, 9, 12 Clock outputs at V level DDL SSON 10 Spread spectrum enable pin 0 = SS off 1 = SS on. Weak pull-up. VDDL 11 3.3 V clock voltage supply VSS 13 Ground REF 14 Reference output at V level DD NC 15 No connect 1 XOUT 16 Crystal output Notes 1. Float XOUT if XIN is externally driven. Document Number: 38-07350 Rev. *E Page 2 of 9