CY62158EV30LL-45ZSXI Infineon

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62158EV30 MoBL 8-Mbit (1024K 8) Static RAM 8-Mbit (1024K 8) Static RAM Features Functional Description Very high speed: 45 ns The CY62158EV30 is a high performance CMOS static RAM organized as 1024K words by 8 bits. This device features Wide voltage range: 2.20 V3.60 V advanced circuit design to provide ultra low active current. This Pin compatible with CY62158DV30 is ideal for providing More Battery Life (MoBL ) in portable applications such as cellular telephones. The device also has an Ultra low standby power automatic power down feature that significantly reduces power Typical standby current: 2 A consumption. Placing the device into standby mode reduces Maximum standby current: 8 A power consumption significantly when deselected (CE HIGH or 1 CE LOW). The eight input and output pins (I/O through I/O ) Ultra low active power 2 0 7 are placed in a high impedance state when the device is Typical active current: 6 mA at f = 1 MHz deselected (CE HIGH or CE LOW), the outputs are disabled 1 2 Easy memory expansion with CE , CE , and OE features 1 2 (OE HIGH), or a write operation is in progress (CE LOW and 1 CE HIGH and WE LOW). 2 Automatic power down when deselected To write to the device, take Chip Enables (CE LOW and CE 1 2 CMOS for optimum speed/power HIGH) and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O through I/O ) is then written into the location specified Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II 0 7 on the address pins (A through A ). packages 0 19 To read from the device, take Chip Enables (CE LOW and CE 1 2 HIGH) and OE LOW while forcing the WE HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. See Truth Table on page 11 for a complete description of read and write modes. For a complete list of related documentation, click here. Logic Block Diagram A I/O 0 DATA IN DRIVERS IO 0 0 A 1 A I/O 2 IO 1 1 A 3 A I/O 4 IO 2 2 A 5 A I/O 6 1024K x 8 IO 3 3 A 7 A I/O 8 ARRAY IO 4 4 A 9 A I/O 10 IO 5 5 A 11 A I/O 12 IO 6 6 CE 1 I/O IO 7 CE POWER 7 2 COLUMN DECODER WE DOWN OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05578 Rev. *M Revised February 28, 2020 ROW DECODER A 13 A 14 A 15 A 16 A 17 A 18 A 19 SENSE AMPS