CY7C1312KV18-333BZC

CY7C1312KV18/CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports CY7C1312KV18 1M 18 Supports concurrent transactions CY7C1314KV18 512K 36 333 MHz clock for high bandwidth Functional Description Two-word burst on all accesses The CY7C1312KV18, and CY7C1314KV18 are 1.8 V Double-data rate (DDR) interfaces on both read and write ports Synchronous Pipelined SRAMs, equipped with QDR II (data transferred at 666 MHz) at 333 MHz architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The Two input clocks (K and K) for precise DDR timing read port has dedicated data outputs to support read operations SRAM uses rising edges only and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and Two input clocks for output data (C and C) to minimize clock data outputs to completely eliminate the need to turnaround the skew and flight time mismatches data bus that exists with common I/O devices. Access to each Echo clocks (CQ and CQ) simplify data capture in high-speed port is through a common address bus. Addresses for read and systems write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II read and write ports are Single multiplexed address input bus latches address inputs completely independent of one another. To maximize data for both read and write ports throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit Separate port selects for depth expansion words (CY7C1312KV18), or 36-bit words (CY7C1314KV18) that Synchronous internally self-timed writes burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both QDR II operates with 1.5 cycle read latency when DOFF is input clocks (K and K and C and C), memory bandwidth is asserted HIGH maximized while simplifying system design by eliminating bus Operates similar to QDR I device with one cycle read latency turnarounds. when DOFF is asserted LOW Depth expansion is accomplished with port selects, which enables each port to operate independently. Available in 18, and 36 configurations All synchronous inputs pass through input registers controlled by Full data coherency, providing most current data the K or K input clocks. All data outputs pass through output Core V = 1.8 V (0.1 V) I/O V = 1.4 V to V registers controlled by the C or C (or K or K in a single clock DD DDQ DD domain) input clocks. Writes are conducted with on-chip Supports both 1.5 V and 1.8 V I/O supply synchronous self-timed write circuitry. Available in 165-ball FBGA package (13 15 1.4 mm) For a complete list of related documentation, click here. Offered in both Pb-free and non Pb-free packages Variable drive HSTL output buffers JTAG 1149.1 compatible test access port PLL for accurate data placement Selection Guide Description 333 MHz 300 MHz 250 MHz Unit Maximum operating frequency 333 300 250 MHz Maximum operating current 18 690 640 560 mA 36 840 780 670 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-58903 Rev. *K Revised November 28, 2017256 K x 36 Array 512 K x 18 Array 256 K x 36 Array 512 K x 18 Array CY7C1312KV18/CY7C1314KV18 Logic Block Diagram CY7C1312KV18 18 D 17:0 Write Write 19 Address A Reg Reg (18:0) Register 19 Address A (18:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 36 V 18 REF 18 CQ Reg. Reg. Control WPS Logic 18 18 BWS Q Reg. 1:0 17:0 18 Logic Block Diagram CY7C1314KV18 36 D 35:0 Write Write 18 Address A Reg Reg (17:0) Register 18 Address A (17:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 72 V 36 REF 36 CQ Reg. Reg. Control WPS Logic 36 36 BWS Q Reg. 3:0 35:0 36 Document Number: 001-58903 Rev. *K Page 2 of 31 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode